Trench MOS Barrier Schottky Rectifier CMP Planarization
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Solution Overview
Problem
Existing trench MOS barrier Schottky rectifiers face issues with irregular topographies between device structures, leading to increased reverse leakage current, reduced solderability, and plasma damage during fabrication, which affect device performance and manufacturing yields.
Innovation Solution
The implementation of chemical mechanical planarization (CMP) to create a substantially planar surface between shield dielectric, polysilicon, and mesas, along with the use of a solderable top metal layer, reduces topography variations and improves solderability, thereby minimizing reverse leakage current and plasma-induced damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional fabrication techniques are used to form TMBS rectifiers, then device structures are created, but irregular topographies are produced between device structures which increase reverse leakage current
Solution Approach 1:
Chemical mechanical planarization (CMP) is performed on the solderable top metal layer before subsequent fabrication steps to pre-establish a planar surface. This preliminary planarization prevents topography propagation to later-formed layers and eliminates the root cause of increased reverse leakage current, addressing the manufacturing precision issue before it affects device performance
Solution Approach 2:
The patent converts the potentially harmful irregular topographies into a beneficial planar surface through CMP processing. By removing the non-coplanar features that would otherwise increase reverse leakage current, the process transforms a harmful manufacturing defect into an improved device characteristic with lower leakage current
2Reliability
If conventional fabrication techniques are used, then device structures are formed, but non-coplanar surfaces are created which reduce solder connection integrity
Solution Approach 1:
CMP is applied to the solderable top metal layer in advance of soldering operations to pre-establish a coplanar surface. This preliminary action ensures that when solder connections are subsequently made, the surface is uniformly flat, maximizing solder joint integrity and reliability without requiring rework or additional corrective steps
3Ease of manufacture
If irregular topographies exist between polysilicon gates and mesas, then device fabrication proceeds, but plasma damage is induced to the shield dielectric structure
Solution Approach 1:
The solderable top metal layer is planarized using CMP before plasma etching operations. This preliminary planarization eliminates non-coplanar features that would otherwise cause charge build-up and arcing during plasma processing, allowing subsequent plasma etching to proceed without damaging the shield dielectric structure while maintaining ease of manufacture
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in reduced reverse leakage current, enhanced solderability, and increased manufacturing yields by creating a uniform surface and preventing plasma damage, leading to improved performance and reliability of the semiconductor devices.
Implementation Method 1
chemical mechanical planarization (CMP) to create a substantially planar surface between shield dielectric, polysilicon, and mesas
Data Source
AI summary
High Efficiency Diode (HED) rectifiers with improved performance including reduced reverse leakage current, reliable solderability properties, and higher manufacturing yields are fabricated by minimizing topography variation at various stages of fabrication. Variations in the topography are minimized by using a CMP process to planarize the HED rectifier after the field oxide, polysilicon and/or solderable top metal are formed.