Trench MOS Transistor Cell Layout for Lower On-State Losses
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Solution Overview
Problem
Existing power semiconductor devices face challenges in reducing on-state losses, hole drainage, and improving controllability and blocking capability, particularly in IGBTs and MOSFETs, due to limitations in transistor cell designs and gate electrode configurations.
Innovation Solution
The design incorporates multiple transistor cells with a drift layer, first and second base layers, and source regions of specific conductivity types, along with trench gate electrodes and insulating layers, allowing for enhanced electron flow and reduced capacitance by eliminating the planar gate electrode or disconnecting it from the trench gate electrodes, thereby achieving improved on-state performance and controllability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If planar and trench gate electrodes are electrically disconnected or planar gate is omitted, then device capacitance is reduced leading to lower switching losses and improved controllability, but inversion layer formation under planar gate becomes problematic and on-state performance may be affected
Solution Approach 1:
The gate electrode is segmented into planar and trench portions that are electrically disconnected, allowing independent optimization of each segment's function while reducing total device capacitance for lower switching losses
Solution Approach 2:
An insulating layer is introduced as an intermediary between the planar gate electrode and the semiconductor layers, preventing unwanted inversion layer formation while maintaining the beneficial capacitance reduction effect
2Loss of energy
If trench gate electrodes are used with closely packed trenches to achieve very low conduction losses, then on-state voltage drop is reduced, but device complexity and manufacturing precision requirements increase
Solution Approach 1:
The gate structure transitions from traditional planar 2D configuration to a 3D trench-based architecture, enabling closely packed trenches that provide strong barrier to hole drainage while maintaining manufacturability through vertical structuring
3Ease of operation
If planar gate electrode is omitted or disconnected, then overall device capacitance is reduced improving controllability, but electron transport path through planar MOS channel is eliminated requiring alternative conduction paths
Solution Approach 1:
The electron transport mechanism is made dynamic by enabling formation of inversion layers on trench walls that can be controlled through applied voltage, providing adaptive conduction paths that maintain low capacitance while ensuring reliable electron transport
Solution Approach 2:
Electron transport transitions from primarily lateral planar MOS channel to vertical conduction through trench structures, utilizing the third dimension to create alternative low-capacitance transport paths that improve controllability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration results in reduced on-state losses, stable gate parameters, improved blocking capability, and precise control over input capacitance, suitable for both silicon and wide bandgap materials, with the potential for high-density trench recess and simplified manufacturing processes.
Implementation Method 1
an additional MOS channel is formed along the lateral walls of the trench recesses embedding the second gate electrodes
Implementation Method 2
This additional MOS channel is connected in parallel with the planar MOS channel and provide an unobstructed flow path for electrons
Implementation Method 3
electrically insulated from the first base layer, second base layer, source region and the drift layer by a first insulating layer
Implementation Method 4
there will be no capacitance associated with the planar electrodes, so the overall capacitance of the device is reduced
Implementation Method 5
The electrons will flow from the edge of the n source region along the side walls of adjacent trench recesses
Implementation Method 6
which source region has a higher doping concentration than the drift layer
Data Source
AI summary
A Metal Oxide Semiconductor (MOS) transistor cell design has a source region and a first base layer extending in a third dimension. When a control voltage greater than a threshold value is applied on the gate trench, electrons flow from a singular point within the source region, into a radial MOS channel formed on the lateral walls of those trench regions surrounded by the first base layer, but not abutting on the higher doped second base layer. The MOS channel width is determined by a quadrant centred on the singular point and with a radius equal to the separation region between the singular point and the maximum surface doping concentration point in the first base layer.