Trench MOS Transistor Gate Layout for Lower Gate-Drain Capacitance
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Solution Overview
Problem
Existing semiconductor devices, particularly MOS transistors, face challenges in achieving high performance due to trade-offs between on-resistance and switching losses, which are influenced by the capacitance between the gate and drain.
Innovation Solution
The MOS transistor design incorporates a field plate electrode with alternating recess and thinning-out portions, along with a gate electrode configuration that shifts in the trench direction, reducing the gate area and capacitance while optimizing the trench structure to balance on-resistance and switching losses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the gate area is reduced to lower capacitance, then switching losses are reduced, but on-resistance increases
Solution Approach 1:
The gate electrode is segmented into multiple gates disposed at different positions along the trench length direction. Each gate controls a specific region of the channel, allowing independent optimization of capacitance and resistance characteristics. The segmentation enables reduced total gate area (lower capacitance) while maintaining effective channel control (acceptable on-resistance).
Solution Approach 2:
Different gate regions are positioned to control different channel sections with locally optimized characteristics. The first gate controls the upper channel region while the second gate controls the lower channel region, allowing each gate to be sized appropriately for its specific function rather than requiring a uniformly large gate structure.
2Ease of manufacture
If a conventional gate structure is used, then manufacturing is simple, but performance improvement is limited
Solution Approach 1:
The gate electrode is divided into multiple discrete gates along the trench, with each gate formed in a separate recess portion. This segmentation is achieved through standard semiconductor fabrication processes including selective epitaxial growth and etching, maintaining manufacturing simplicity while enabling superior performance through reduced capacitance and optimized current distribution.
Data Source
AI summary
A semiconductor device with high performance is provided. A semiconductor device according to the present disclosure includes a semiconductor substrate having a plurality of trenches provided along a first direction, a field plate electrode having a plurality of recess portions and a plurality of thinning-out portions which are alternately disposed in the first direction, and being provided in the trench, an oxide film provided on the field plate electrode, and a gate electrode formed on the oxide film and disposed in each of the recess portions. In the adjacent trenches, the gate electrodes are disposed to be shifted in the first direction.