Trench Power MOSFET Barrier Layer for Lower Parasitic Capacitance
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Solution Overview
Problem
Existing trench power MOSFETs face a challenge in minimizing parasitic capacitance between the top and bottom electrodes while maintaining the active region area, as forming a thick oxide layer reduces the current due to sidewall oxidation of the trench.
Innovation Solution
A trench power MOSFET design with a barrier layer of silicon nitride, positioned under the top electrode and within a U-shaped structure, prevents sidewall oxidation and allows for a thicker inter-electrode dielectric layer, reducing parasitic capacitance and maintaining the trench width.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a thick oxide layer is formed between the top and bottom electrodes to reduce parasitic capacitance, then the gate capacitance is reduced, but the sidewall of the trench is oxidized and the active region area is reduced
Solution Approach 1:
The patent divides the trench structure into multiple segments with different functions: the top electrode region for gate control, the bottom electrode region for field plate function, and the intermediate region with the thick oxide layer for capacitance reduction. This segmentation allows each region to be optimized independently without compromising the others.
Solution Approach 2:
The patent introduces an intermediary structure (the thick oxide layer formed in the gap between electrodes) that mediates between the top and bottom electrodes. This intermediary layer reduces parasitic capacitance while the selective oxidation process mediates between the need for thick oxide and the need to preserve active region area.
2Reliability
If the gap between the trench and top electrode is increased to reduce parasitic capacitance, then the gate-drain capacitance is reduced, but the device area increases
Solution Approach 1:
The patent transitions from increasing horizontal gap distance to increasing vertical oxide layer thickness as the primary method for reducing parasitic capacitance. This dimensional shift allows capacitance reduction without proportionally increasing the device footprint, as the thick oxide layer is formed within the existing trench structure rather than requiring additional lateral space.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces parasitic capacitance and enhances switching speed by maintaining the trench width and preventing sidewall oxidation, thereby improving the performance of the trench power MOSFET.
Implementation Method 1
forming a first oxide layer on a sidewall of the trench, forming an barrier layer on the first oxide layer
Implementation Method 2
an barrier layer disposed on the first oxide layer... The barrier layer is formed of a material different from materials of the first and second oxide layers
Data Source
AI summary
A trench power MOSFET includes a body region disposed on a semiconductor substrate, a trench passing through the body region, an top electrode and a bottom electrode spaced apart from each other in a vertical direction in the trench, an inter-electrode dielectric layer disposed between the top electrode and the bottom electrode, and a plurality of dielectric layers, disposed between a sidewall of the trench and the bottom electrode, comprising a first oxide layer disposed on the sidewall of the trench, an barrier layer disposed on the first oxide layer, and a second oxide layer disposed on the barrier layer. The barrier layer is formed of a material different from materials of the first and second oxide layers.