Trench MOSFET Structure for Precise Parasitic Capacitance Reduction
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Solution Overview
Problem
Existing semiconductor devices, such as trench type MOSFETs, face challenges in reducing parasitic capacitance with high accuracy, which affects switching speed and efficiency, especially when operating at high voltages, and existing techniques either fail to reduce capacitance effectively or introduce additional issues like gate voltage oscillation.
Innovation Solution
The semiconductor device incorporates a configuration with a first and second conductivity type semiconductor parts, including a drift layer, base region, source region, and protective layers, with trenches and sidewall connection layers to accurately reduce parasitic capacitance by altering the capacitance types and connections between electrodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a protective layer is provided in the bottom portion of the trench to prevent electrical field concentration, then reliability is improved, but parasitic capacitance increases and switching speed decreases
Solution Approach 1:
The protective layer is segmented into two distinct types: a first protective layer at the bottom portion of the trench and a second protective layer in the middle portion. This segmentation allows each layer to serve specific functions - the first layer prevents electrical field concentration at the critical bottom region, while the second layer reduces parasitic capacitance without compromising the reliability benefit of the first layer.
Solution Approach 2:
Different protective layers are applied to different regions of the trench based on local requirements. The bottom portion receives a protective layer optimized for electrical field management, while the middle portion receives a protective layer optimized for capacitance reduction. This local differentiation resolves the contradiction by tailoring the protective function to specific spatial needs within the trench structure.
2Loss of energy
If the gate electrode is divided vertically with an insulating film to reduce Cgd, then parasitic capacitance is reduced, but manufacturing complexity increases
Solution Approach 1:
A second protective layer acts as an intermediary element between the gate electrode and the semiconductor layers. This intermediary structure reduces the gate-drain capacitance (Cgd) by providing electrical isolation in the middle portion of the trench, thereby reducing switching loss without requiring direct modification or division of the gate electrode itself, thus avoiding increased manufacturing complexity.
3Productivity
If the operation frequency is increased to downsize the inverter circuit, then productivity is improved, but switching loss increases due to higher switching frequency
Solution Approach 1:
The protective layers modify the electrical parameters of the MOSFET by reducing parasitic capacitance values. This parameter change allows the device to operate at higher frequencies with reduced switching loss, as the reduced capacitance decreases the energy required for each switching transition, thereby enabling high-frequency operation that downsizes the inverter circuit without proportionally increasing total switching loss.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables precise reduction of parasitic capacitance, enhancing switching speed and efficiency while preventing electrical field concentration, thus improving the overall performance of the semiconductor device.
Implementation Method 1
A parasitic capacitance of the MOSFET significantly involves the switching loss. The parasitic capacitance of the MOSFET includes three types of capacitance, that is, a drain-source capacitance (Cds), a gate-drain capacitance (Cgd), and a gate-source capacitance (Cgs).
Implementation Method 2
the trench type MOSFET for controlling the electrical power has a problem that an electrical field is concentrated in a bottom portion of the trench, thereby easily leading to a breakdown of a gate oxide film
Implementation Method 3
a depletion layer can be expanded from the protective layer to the substrate, and as a result, the electrical field in the bottom portion of the trench can be reduced
Implementation Method 4
An insulated gate type semiconductor devices such as an insulated gate bipolar transistor (IGBT) and a metal oxide semiconductor field effect transistor (MOSFET) are widely used as a switching element controlling a power supply to a load such as a motor
Data Source
AI summary
An object is to provide a technique capable of reducing a parasitic capacitance in a semiconductor device with high accuracy. A semiconductor device includes: a base region; a source region; a second trench passing through the base region to reach the drift layer; a second protective layer disposed in a bottom portion of the second trench; a source electrode, at least part of which is disposed in the second trench, to be electrically connected to a first protective layer, the base region, and the source region; and a source side connection layer of a second conductivity type constituting at least part of a lateral portion of the second trench and connected to the base region and the second protective layer.