Trench Power MOSFET Compensation Layer Design
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Solution Overview
Problem
Trench power MOSFETs face challenges in achieving low on-state resistance while avoiding short-channel effects and high subthreshold slope, particularly when reducing channel length leads to increased doping concentrations that degrade mobility and shift threshold voltage.
Innovation Solution
Incorporating a compensation layer of the same conductivity type as the source layer between the gate insulation layer and the substrate layer, with a thickness ranging from 1 nm to 10 nm, and a high doping concentration to satisfy the inequality Lch > 4√(εCR*tCOMP/εGI), which helps in determining the channel length and reducing short-channel effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the channel length is reduced to achieve low on-state resistance, then the drive capability is improved, but short-channel effects occur and threshold voltage shifts
Solution Approach 1:
The patent introduces a compensation layer with specific doping concentration (1×10^18 to 1×10^19 atoms/cm³) and thickness (1 nm to 10 nm) located adjacent to the channel region. This localized structural modification creates different electrical properties in different regions of the device, allowing the channel to maintain low resistance while the compensation layer prevents short-channel effects and stabilizes threshold voltage.
2Loss of energy
If the channel length is reduced to decrease on-state losses, then the on-state resistance is lowered, but subthreshold slope increases
Solution Approach 1:
The compensation layer acts as an intermediary structure between the channel region and the drain region. It mediates the electrical field distribution and carrier flow, allowing the short channel to achieve low on-state losses while the compensation layer maintains proper subthreshold slope characteristics through its specific doping profile and position.
3Reliability
If the doping concentration is increased to prevent punch-through, then the reverse blocking capability is improved, but carrier mobility decreases
Solution Approach 1:
The patent optimizes the doping concentration parameter of the compensation layer to a specific range (1×10^18 to 1×10^19 atoms/cm³) and thickness (1 nm to 10 nm). This parameter optimization allows the device to achieve adequate reverse blocking capability while maintaining high carrier mobility in the channel region, avoiding the trade-off that would occur with higher doping concentrations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces on-state losses, maintains low subthreshold slope, and optimizes threshold voltage, even with short channel lengths, by efficiently managing channel carrier mobility and preventing punch-through at high reverse voltages.
Implementation Method 1
an n-doped source region through a channel region in the p-doped body region adjacent to the trenches to an n-doped drift region by the field effect
Implementation Method 2
there is formed a gate dielectric and a gate electrode to control the current conduction from an n-doped source region through a channel region
Data Source
Figure 1~2
Figure 3A~3B
Figure 3C~3D
AI summary
It is an object of the invention to provide a power semiconductor device having a low on-state resistance while avoiding any short channel effects and having a low subthreshold slope. To attain this object the invention provides a trench power semiconductor device, which comprises a compensation layer (15) of a first conductivity type, wherein the compensation layer (15) is extending on a gate insulation layer (11) between a source layer (5) of the first conductivity type and a substrate layer (9) of the first conductivity type directly adjacent to a channel region of a second conductivity type, and wherein: Lch > 4 √( (εcrtcomptGI)). In the above inequation Lch is a channel length, εCR is a permittivity of the channel region, εGI is a permittivity of the gate insulation layer, tC0MP is a thickness of the compensation layer (15) and tGI is a thickness of the gate insulation layer (11).