Trench MOSFET Layout Without Source Contact Holes
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Solution Overview
Problem
Conventional trench field effect transistors face challenges in reducing cell dimensions and achieving equal-potential electrical lead-out of the body region and source without forming contact holes, which limits their performance and increases the risk of premature breakdown.
Innovation Solution
A manufacturing method that employs self-aligned source implantation using a source implantation mask to form a body region lead-out region, allowing direct electrical lead-out of the source and body region without contact holes, thereby enabling further reduction in cell dimensions and increasing trench density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the lateral spacing of cells is reduced to increase cell density, then the on-resistance decreases, but the capability of lithography and etching machines limits further reduction
Solution Approach 1:
The patent transitions from a conventional planar layout to a three-dimensional trench structure. By forming vertical trenches in the semiconductor substrate and placing gate electrodes within these trenches, the invention utilizes the vertical dimension to achieve higher channel density without further reducing the lateral cell spacing. This dimensional transition allows continued performance improvement despite lithography and etching limitations.
2Manufacturing precision
If a square layout closed-loop structure is used to increase channel density, then the on-resistance decreases, but sufficient space is required for forming contact holes to lead out body region and source
Solution Approach 1:
The invention moves the lead-out function from the lateral plane to the vertical dimension by forming contact holes that extend through the trench structure. The source and body region are electrically connected to external contacts via vertical pathways through the trenches, eliminating the need for additional lateral space dedicated to contact hole formation in the conventional plane.
Solution Approach 2:
The patent merges the functions of the body region lead-out and source lead-out into a unified trench structure. Both regions are contained within and led out through the same vertical trench pathways, consolidating what would traditionally require separate lateral contact structures into a single integrated three-dimensional architecture.
3Productivity
If cell dimension is reduced to increase trench density, then the on-resistance decreases, but it becomes difficult to form contact holes to lead out body region and source with equal potential
Solution Approach 1:
By transitioning to vertical trench structures, the invention achieves higher effective trench density within the same lateral footprint. The vertical orientation of trenches allows closer lateral spacing while maintaining adequate vertical space for proper contact hole formation and equal-potential lead-out of body region and source through the trench structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for continued reduction in cell dimensions, increased trench density, reduced on-resistance, improved switching speed, and prevention of premature device breakdown by ensuring equal-potential electrical lead-out of the source and body region.
Implementation Method 1
performing ion implantation on the epitaxial layer to form a body region in the implantation region
Data Source
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AI summary
Provided are a trench field effect transistor structure and a manufacturing method. The manufacturing method comprises: providing a semiconductor substrate, forming an epitaxial layer, a first trench, a second trench, a first gate dielectric layer, a first gate structure, a second gate dielectric layer, a second gate structure, and a bulk region, forming a source implantation mask, forming, by performing ion implantation on the basis of the mask, a source, and forming a source electrode structure. The invention performs self-aligned source implantation by designing the source implantation mask, and forms a lead-out region of the bulk region while forming the source, thereby enabling direct lead-out of the source and the bulk region. The invention uses a self-alignment technique to further reduce the cell dimension, and enables equal-potential electrical lead-out of the source and the bulk region without providing a source contact hole. The invention is specifically applicable to square trench field effect transistors having a closed-loop structure, and addresses, from the process and the layout, a bulk region lead-out problem caused by a reduced cell dimension, thereby preventing pre-mature device breakdown.