Trench Power MOSFET Gate Segmentation for Capacitance Reduction
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Solution Overview
Problem
Current power MOSFETs with high intrinsic gate-to-drain capacitance (Cgd) limit switching speed, making them unsuitable for high-frequency circuits due to increased switching loss.
Innovation Solution
A trench power semiconductor device and manufacturing method that form a PN junction in the gate, reducing effective capacitance between the gate and drain by incorporating a gate insulating layer, a laminated layer, and doped semiconductor structures, with a thermal diffusion process to create a PN junction between the upper and lower doped regions, thereby reducing junction capacitance and parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If a conventional power MOSFET structure is used, then the device can be manufactured with standard processes, but the intrinsic gate-to-drain capacitance is too high which increases switching loss and limits switching speed
Solution Approach 1:
The gate structure is segmented into multiple doped regions (first heavily doped semiconductor structure and two second heavily doped semiconductor structures) with different doping types and concentrations. This segmentation creates a complex doping profile that forms a PN junction, reducing the gate-to-drain capacitance by dividing the charge distribution across multiple regions rather than having a single high-capacitance interface.
Solution Approach 2:
Different regions of the gate structure are assigned different local properties through selective doping. The first heavily doped semiconductor structure has a first conductive impurity while the second heavily doped semiconductor structures have a second conductive impurity. This local quality variation creates the PN junction effect that reduces capacitance in critical areas while maintaining overall device functionality.
2Speed
If the intrinsic gate-to-drain capacitance is reduced by modifying the gate structure, then switching speed improves, but the device complexity increases due to multiple doped regions and thermal diffusion processes
Solution Approach 1:
The gate structure is prepared with pre-formed doped regions (first and second heavily doped semiconductor structures) before the final thermal diffusion process. The preliminary doping establishes the foundation for the PN junction, and the subsequent thermal diffusion process completes the junction formation in a single step, reducing the need for multiple complex processing steps.
Solution Approach 2:
The formation of the PN junction is merged with the gate structure fabrication process. The thermal diffusion process simultaneously creates the PN junction between the first and second heavily doped semiconductor structures while completing the gate formation, combining multiple functions into a single integrated process step.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces the effective capacitance between the gate and drain, minimizing switching loss and enhancing switching speed, making the trench power semiconductor device more suitable for high-frequency applications.
Implementation Method 1
a thermal diffusion process is performed, so that the first surface doped region forms a source region, and a gate is formed in the trench
Implementation Method 2
a doping process is performed, in which a second conductive impurity is implanted into the body region to form a first surface doped region and to form a second surface doped region on the top of the first heavily doped semiconductor structure simultaneously
Data Source
AI summary
A trench power semiconductor device and a manufacturing method thereof are provided. The trench power semiconductor device includes a substrate, an epitaxial layer disposed on the substrate, and a gate structure. The epitaxial layer has at least one trench formed therein, and the gate structure is disposed in the trench. A gate structure includes a lower doped region and an upper doped region disposed above the lower doped region to form a PN junction. The concentration of the impurity decreases along a direction from a peripheral portion of the upper doped region toward a central portion of the upper doped region.