Trench MOSFET Gate Oxide Profiling for Void and Leakage Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing methods for forming a metal oxide semiconductor field effect transistor (MOSFET) with a gate trench structure face challenges in maintaining uniform doping concentrations and forming void-free gates due to the complexity of ion implantation processes and surface roughness during trench formation.
Innovation Solution
The method involves forming shielding and well regions before creating the trench, followed by a thermal oxidation process to form a thicker gate dielectric layer with a curved sidewall, ensuring uniform doping concentrations and smoother surfaces, which are then filled with a conductive material to form a wider and void-reduced gate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If ion implantation is performed after trench formation to form shielding and well regions, then doping concentration can be adjusted, but the process complexity increases and surface roughness occurs
Solution Approach 1:
The shielding region and well region are formed by ion implantation before the trench is etched, rather than after. This preliminary action allows the doping to occur on a flat surface, avoiding the complexity and surface roughness issues associated with post-trench ion implantation, while still achieving the desired doping concentration uniformity in the final device structure
Solution Approach 2:
The conventional sequence of operations is inverted: instead of forming the trench first and then performing ion implantation to create the shielding and well regions, the patent performs ion implantation to form these doped regions first, then etches the trench. This inversion of the process sequence resolves the technical contradiction by eliminating the surface roughness and process complexity issues
2Ease of manufacture
If a uniform gate dielectric layer is formed in the trench, then manufacturing is simplified, but leakage current increases due to insufficient thickness at the source region
Solution Approach 1:
The gate dielectric layer is formed with non-uniform thickness through a selective oxidation process where the source region, having higher doping concentration, oxidizes faster and forms a thicker dielectric layer. This local quality variation ensures sufficient dielectric thickness at the source region to prevent leakage current while maintaining manufacturability through a standard oxidation process
Solution Approach 2:
The patent utilizes the doping concentration parameter difference between the source region and other areas to control the oxidation rate. The higher doping concentration in the source region causes faster oxidation, automatically creating the required thickness variation in the gate dielectric layer without complex deposition processes, thus balancing ease of manufacture with leakage current control
3Manufacturing precision
If the trench has vertical walls for precise gate alignment, then gate positioning is improved, but void formation occurs during gate filling
Solution Approach 1:
The trench walls are formed with curvature rather than vertical straight walls. This curvature, created by the thermal oxidation process that forms the gate dielectric layer, allows the subsequent gate filling process to proceed without void formation. The curved geometry enables better material flow and consolidation during filling while still maintaining precise gate alignment through the controlled oxidation process
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach maintains uniform doping concentrations and reduces voids in the gate, enhancing the semiconductor device's performance by minimizing leakage current and improving channel density.
Implementation Method 1
performing a thermal oxidation process to the sidewall and the bottom of the trench to form a thermal oxidation layer at the sidewall and the bottom of the trench
Implementation Method 2
a thickness of the gate dielectric layer along the source region is greater than a thickness of the gate dielectric layer along the well region
Data Source
AI summary
A method of manufacturing a semiconductor device includes forming a shielding region, well region, and a source region in a drift layer, in which the source region is over the well region, a top of the shielding region is lower than a bottom of the well region, and at least a portion of the shielding region does not overlap the well region, forming a trench in the drift layer, the trench exposing the shielding region, forming a gate dielectric layer at a sidewall and a bottom of the trench, in which a thickness of the gate dielectric layer along the source region is greater than a thickness of the gate dielectric layer along the well region, and forming a gate in the trench.