Bottom-Source Trench MOSFET Gate Charge Reduction
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Solution Overview
Problem
As semiconductor devices are scaled down, maintaining low on resistance, low gate charge, and high breakdown voltage in power transistors becomes challenging, especially in high voltage and current applications, where conventional trench MOS transistors face limitations in gate charge capacitance and switching losses.
Innovation Solution
The design of a bottom-source trench power MOSFET with split gate regions and a field plate reduces gate charge capacitance by insulating gate regions with dielectric layers, improving switching losses and integrating with existing lateral device fabrication processes to reduce costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional trench MOS transistor structure is used, then manufacturing process is simple, but gate charge capacitance is high and switching losses increase
Solution Approach 1:
The gate structure is divided into multiple separate gate electrodes (first gate electrode, second gate electrode, third gate electrode) positioned at different locations within the trench. This segmentation allows each gate electrode to control specific regions independently, reducing the overall gate charge capacitance while maintaining effective channel control, thereby reducing switching losses without excessive complexity increase
Solution Approach 2:
The patent transitions from a conventional planar gate structure to a three-dimensional trench gate structure with multiple gate electrodes arranged vertically and horizontally within the trench. This dimensional change enables better electric field distribution and reduced gate-to-drain capacitance, effectively reducing switching losses while the modular arrangement keeps manufacturing complexity manageable
2Productivity
If semiconductor process node is shrunk, then integration density improves, but maintaining low on resistance and high breakdown voltage becomes difficult
Solution Approach 1:
The patent employs a vertical trench gate structure that extends deep into the semiconductor substrate, utilizing the vertical dimension to achieve high integration density while maintaining effective control over the channel. The multiple gate electrodes at different depths provide distributed control that maintains breakdown voltage characteristics even as device dimensions are scaled down
Solution Approach 2:
Different regions of the device are optimized with specific doping concentrations and gate electrode configurations. The drift region has specific doping levels for breakdown voltage control, while the channel region is optimized for low on-resistance. This local optimization allows the device to maintain high breakdown voltage and low on-resistance despite scaling to smaller process nodes
3Productivity
If semiconductor process node is shrunk, then integration density improves, but maintaining low on resistance becomes difficult
Solution Approach 1:
The channel region is divided into multiple segments controlled by separate gate electrodes, allowing each segment to be independently optimized. This segmentation enables better current distribution and reduces the overall on-resistance by creating multiple parallel conduction paths, while the compact trench structure maintains high integration density
Solution Approach 2:
The patent optimizes doping concentrations, gate electrode dimensions, and trench depth parameters to achieve low on-resistance at scaled dimensions. By carefully adjusting these parameters in the vertical trench structure, the device maintains low on-resistance while achieving high integration density through vertical stacking
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances the performance of power MOSFETs by reducing gate charge capacitance and switching losses, while allowing integration with existing fabrication processes, thus addressing the challenges of scaling down semiconductor devices effectively.
Implementation Method 1
insulating gate regions with dielectric layers
Data Source
AI summary
A method comprises providing a substrate with a second conductivity type, growing a first epitaxial layer having the second conductivity type, growing a second epitaxial layer having a first conductivity type, forming a trench in the first epitaxial layer and the second epitaxial layer, forming a gate electrode in the trench, applying an ion implantation process using first gate electrode as an ion implantation mask to form a drain-drift region, forming a field plate in the trench, forming a drain region in the second epitaxial layer, wherein the drain region has the first conductivity type and forming a source region in the first epitaxial layer, wherein the source region has the first conductivity type, and wherein the source region is electrically coupled to the field plate.