Trench MOSFET Gate Segmentation for Lower Switching Loss
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Solution Overview
Problem
Conventional power semiconductor devices, such as MOSFETs, experience high switching losses due to large input capacitance, which increases turn-on and turn-off times, reducing efficiency, especially at high frequencies.
Innovation Solution
The semiconductor device incorporates a gate trench structure with discrete gate polycrystalline silicon layers isolated by an oxide layer, reducing the overlapping area and capacitance, allowing for faster switching by grounding the second gate polycrystalline silicon and substrate metal to enhance depletion efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the overlapping areas between the polycrystalline silicon and the body region of the second conductive type and the pillar of the first conductive type increase, then the input capacitance Ciss increases, but the turn-on time and turn-off time of the device increase and the switching loss increases
Solution Approach 1:
The gate polycrystalline silicon is segmented into two distinct layers: first gate polycrystalline silicon and second gate polycrystalline silicon, separated by an oxide layer. This segmentation allows independent optimization of each layer's function, reducing the overall overlapping area with the body region and pillar, thereby decreasing input capacitance and switching loss while maintaining reliability
Solution Approach 2:
The second gate polycrystalline silicon layer is extracted and separated from the first gate polycrystalline silicon by an oxide layer. This extraction reduces the harmful overlapping area between the gate structure and the body region/pillar, directly reducing the input capacitance Ciss and subsequent switching losses
2Reliability
If the overlapping areas between the polycrystalline silicon and the body region of the second conductive type and the pillar of the first conductive type increase, then the input capacitance Ciss increases, but the turn-on time and turn-off time of the device increase
Solution Approach 1:
The gate structure is segmented into two isolated polycrystalline silicon layers, reducing the total overlapping area with charge storage regions. This segmentation decreases the input capacitance Ciss, allowing faster charging and discharging of the gate, thereby reducing turn-on and turn-off times
Solution Approach 2:
An oxide layer is introduced as an intermediary between the first and second gate polycrystalline silicon layers. This intermediary isolates the second layer from direct electrical contact with the body region and pillar, reducing parasitic capacitance effects and enabling faster switching transitions
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design reduces switching losses by minimizing turn-on and turn-off times, improving the overall efficiency of the device and reducing energy consumption.
Implementation Method 1
The first gate polycrystalline silicon and the second gate polycrystalline silicon are isolated by an oxide layer. The first gate polycrystalline silicon is insulated from the second gate polycrystalline silicon.
Implementation Method 2
A heavily doped source region of the first conductive type and a heavily doped source region of the second conductive type are arranged in the body region of the second conductive type. The source region of the first conductive type is electrically connected to a substrate metal. The source region of the second conductive type is electrically connected to a source metal.
Implementation Method 3
An epitaxial layer of the first conductive type is provided on the silicon substrate of the first conductive type.
Data Source
AI summary
A semiconductor device for reducing a switching loss includes a drain metal. A silicon substrate of a first conductive type is provided on the drain metal. An epitaxial layer of the first conductive type is provided on the silicon substrate of the first conductive type. A pillar of the first conductive type and a pillar of a second conductive type are arranged in the epitaxial layer of the first conductive type. A body region of the second conductive type is provided on a surface of each pillar. A heavily doped source region of the first conductive type and a heavily doped source region of the second conductive type are arranged in the body region of the second conductive type. A gate trench is formed in the pillar of the first conductive type. Discrete gate polycrystalline silicon is provided in the gate trench.