Trench MOSFET Impurity Layout for Lower On-Resistance
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Solution Overview
Problem
Reducing the pitch of the gate trench in semiconductor devices like power MOSFETs leads to the laterally expanded column region contacting the gate trench, hindering the current path and increasing on-resistance.
Innovation Solution
A semiconductor device structure where a third impurity region of higher impurity density is formed at the bottom of the gate trench, allowing the column region to be deeper and preventing contact with the gate trench, even when the pitch is reduced.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the pitch of the gate trench is reduced to lower on-resistance, then the chip area can be reduced, but the laterally expanded column region contacts the gate trench and hinders the current path
Solution Approach 1:
The patent applies preliminary action by forming a protective insulating film layer on the gate trench before forming the column region. This insulating film is deposited in advance to prevent contact between the laterally expanded column region and the gate trench, ensuring current path integrity even when the gate trench pitch is reduced for smaller chip area.
Solution Approach 2:
The patent uses an insulating film as an intermediary layer between the gate trench and the column region. This intermediate layer physically separates the two structures, preventing direct contact that would hinder the current path, while still allowing the gate trench pitch to be reduced for compact design.
2Productivity
If the pitch of the gate trench is reduced to improve device characteristics, then more gate trenches can be packed in the same area, but the column region expands laterally and contacts the gate trench
Solution Approach 1:
The insulating film is formed on the gate trench structure before the column region is created. This preliminary protective layer prevents the laterally expanding column region from contacting the gate trench, allowing the pitch to be reduced for improved device characteristics without compromising the column region geometry.
Solution Approach 2:
The insulating film serves as a mediator that allows closer spacing of gate trenches while preventing harmful contact with the column region. This intermediary layer enables higher productivity through improved device characteristics while maintaining proper column region shape and separation.
3Manufacturing precision
If ion implantation is used to form the column region, then precise doping can be achieved, but the ion implantation mask cannot be miniaturized further and impurities diffuse during heat treatment
Solution Approach 1:
The patent extracts the protective function from the ion implantation mask process by separately forming an insulating film on the gate trench. This separates the doping precision function from the mask miniaturization challenge, allowing precise doping through ion implantation while the insulating film handles the protection function independently.
Solution Approach 2:
The insulating film acts as an intermediary that replaces the need for complex mask structures. Instead of miniaturizing the ion implantation mask further, the insulating film provides the necessary protection during heat treatment, simplifying the overall device complexity while maintaining doping precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces on-resistance by maintaining the current path integrity and allows for a smaller chip area due to reduced pitch, while also lowering resistance values.
Implementation Method 1
gate electrodes embedded in the first gate trench and the second gate trench via gate insulating film respectively
Implementation Method 2
forming a third impurity region of the first conductivity type formed in the first impurity region covered a bottom portion of the first gate trench
Data Source
AI summary
A semiconductor device has an impurity region covering a bottom of a gate trench and a column region. A bottom of the column region is deeper than a bottom of the gate trench. The impurity region is arranged between the gate trench and the column region. This structure can improve the characteristics of the semiconductor device.