Trench MOSFET Structure Using Phosphosilicate Glass for Source Diffusion
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Solution Overview
Problem
Current trench MOSFET devices face challenges in achieving smaller pitch or cell size and lower on-resistance per unit area due to limitations in source region formation and dopant distribution.
Innovation Solution
The introduction of a trench-gated MOSFET structure with a dielectric layer at the bottom and sides, a phosphosilicate glass layer above the gate conductor, and phosphorus-doped polysilicon layer, along with source and body diffusions of opposite conductivity types adjacent to the trench sidewall, allows for improved control of carrier inversion and reduced on-resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If source regions are formed by implanting dopant species in conventional trench MOSFET devices, then the source regions can be created, but the pitch or cell size cannot be reduced further and on-resistance per unit area remains high
Solution Approach 1:
A phosphosilicate glass (PSG) layer is introduced as an intermediary between the gate conductor and the doped polysilicon layer. This PSG layer serves as a diffusion barrier and mediator that enables precise dopant distribution control during thermal processing, allowing source regions to be formed with greater precision while enabling reduced pitch and lower on-resistance per unit area
Solution Approach 2:
The invention uses a composite structure combining phosphosilicate glass layer with doped polysilicon layer. The PSG layer (containing phosphorus dopant) is positioned below the doped polysilicon layer, creating a composite material system that provides controlled dopant diffusion and precise source region formation, enabling smaller pitch and improved device performance
2Reliability
If the dopant distribution is not optimized, then the fabrication process is simpler, but the on-resistance per unit area remains high
Solution Approach 1:
The invention optimizes dopant distribution by introducing a phosphosilicate glass layer with specific phosphorus concentration, positioned at a controlled thickness (e.g., 50-200 nm) below the doped polysilicon layer. This parameter optimization enables precise control of source region doping profiles, achieving lower on-resistance per unit area while maintaining manageable fabrication complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables the fabrication of DMOS transistors with smaller pitch and lower on-resistance per unit area, enhancing the performance and density of semiconductor devices.
Implementation Method 1
Source and body diffusions of opposite conductivity types are positioned adjacent to a sidewall of the trench
Implementation Method 2
The gate is capacitively coupled to the semiconductor material to control inversion of a portion of the body region
Data Source
AI summary
A vertical-current-flow device includes a trench which includes an insulated gate and which extends down into first-conductivity-type semiconductor material. A phosphosilicate glass layer is positioned above the insulated gate and a polysilicon layer is positioned above the polysilicate glass layer. Source and body diffusions of opposite conductivity types are positioned adjacent to a sidewall of the trench. A drift region is positioned to receive majority carriers which have been injected by the source, and which have passed through the body diffusion. A drain region is positioned to receive majority carriers which have passed through the drift region. The gate is capacitively coupled to control inversion of a portion of the body region. As an alternative, a dielectric layer may be used in place of the doped glass where permanent charge is positioned in the dielectric layer.