Self-Aligned Contacts in High Density Trench MOSFETs
Solution Overview
Problem
Existing high-density trench-based power MOSFETs face challenges in minimizing on-resistance (RdsA) and maximizing switching speed for low voltage load switching and high frequency DC-DC applications, particularly due to issues with charge balancing, high electric fields, and scalability limitations.
Innovation Solution
The development of self-aligned source and body contacts using insulative spacers and a two-step gate oxide structure, which reduces voltage burden on the epitaxial layer and allows for increased doping concentration, thereby decreasing RdsA and enhancing switching speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If trench-based MOSFET design is used to reduce cell pitch, then device density is improved, but on-resistance increases due to lack of charge balancing and high electric fields
Solution Approach 1:
The gate oxide is divided into two distinct regions: a first gate oxide region with greater thickness and a second gate oxide region with lesser thickness. This segmentation allows different portions of the device to have optimized electrical characteristics, with the thicker region providing charge balancing and the thinner region enabling lower resistance paths.
Solution Approach 2:
Different gate oxide thicknesses are applied to different spatial regions of the device. The first gate oxide region (thicker) is positioned to provide charge balancing in specific areas, while the second gate oxide region (thinner) is positioned to reduce resistance in other areas, creating local optimization of electrical properties throughout the device structure.
2Reliability
If thin gate oxide is used to reduce on-resistance, then conductivity is improved, but breakdown voltage decreases due to high electric fields
Solution Approach 1:
The gate oxide structure implements local quality by having a first gate oxide region with greater thickness for voltage support and a second gate oxide region with lesser thickness for conductivity enhancement. This spatial variation in oxide thickness allows the device to simultaneously achieve high breakdown voltage and low on-resistance.
Solution Approach 2:
The gate oxide is segmented into two functional regions with different thicknesses. The thicker first gate oxide region handles the high voltage stress, while the thinner second gate oxide region provides low resistance conduction paths, effectively dividing the electrical stress management functions.
3Strength
If thicker gate oxide is used to support blocking voltage, then breakdown voltage is improved, but on-resistance increases
Solution Approach 1:
The patent applies local quality by positioning a thicker first gate oxide region in areas requiring voltage support and a thinner second gate oxide region in areas requiring high conductivity. This localized optimization allows the device to achieve both high breakdown voltage and low on-resistance simultaneously.
4Productivity
If cell pitch is reduced to increase device density, then productivity is improved, but manufacturing precision becomes more difficult
Solution Approach 1:
The gate oxide formation process is segmented into two distinct deposition or growth steps, allowing independent control of each oxide region's thickness. This segmentation simplifies the manufacturing precision requirements compared to attempting to control a single uniform oxide thickness, as each region can be optimized separately.
Data Source
AI summary
Aspects of the present disclosure describe a high density trench-based power MOSFET with self-aligned source contacts. The source contacts are self-aligned with a first insulative spacer and a second insulative spacer, wherein the first spacer is resistant to an etching process that will selectively remove the material the second spacer is made from. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.