Trench MOSFET Self-Alignment for Smaller Cell Pitch
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Solution Overview
Problem
Conventional trench MOSFETs face challenges in reducing specific on-resistance due to limitations in device cell pitch reduction, alignment accuracy, and maintaining stable electrical parameters, primarily because of the constraints in lithography machine exposure capability and alignment accuracy.
Innovation Solution
A trench field effect transistor structure and manufacturing method that employs a self-alignment process to reduce cell unit pitch, improve cell density, and lower device channel resistance, featuring a 'T'-shaped source electrode structure to enhance contact areas and avalanche tolerance, thereby stabilizing electrical parameters and reducing specific on-resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the device cell pitch is reduced to decrease specific on-resistance, then the conduction loss is reduced, but the process production safety window becomes smaller and alignment accuracy requirements become more stringent
Solution Approach 1:
The source contact hole is formed using self-aligned etching where the device trench structure itself serves as the etching mask. This eliminates the need for separate lithography alignment steps, allowing the source contact hole to be automatically positioned relative to the device trench without additional alignment accuracy requirements. The structure serves its own positioning function, enabling cell pitch reduction without proportionally increasing alignment difficulty.
2Productivity
If the device cell pitch is reduced to increase cell density, then the specific on-resistance is reduced, but the lithography machine alignment accuracy cannot ensure sufficient safety distance between source contact hole and device channel
Solution Approach 1:
The device trench structure automatically defines the position of the source contact hole through self-aligned etching, ensuring a predetermined safety distance is maintained between the source contact hole bottom and the device channel. This self-positioning mechanism eliminates reliance on lithography alignment accuracy, allowing cell density to be increased by reducing cell pitch while maintaining electrical parameter stability through guaranteed geometric relationships.
3Manufacturing precision
If traditional lithography process is used to maintain process production safety window, then alignment accuracy is maintained, but the device cell pitch cannot be continuously reduced
Solution Approach 1:
The process replaces lithography-based alignment with self-aligned etching where the device trench structure itself defines the source contact hole position. This eliminates the need for high-precision lithography alignment, allowing device cell pitch to be continuously reduced without being constrained by lithography machine capabilities. The structure automatically ensures proper positioning, making the process independent of lithography alignment accuracy limitations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The approach allows for a stable electrical parameter and low specific on-resistance in trench MOSFETs, overcoming previous limitations by enabling further reduction in cell unit pitch and improving alignment accuracy without relying on traditional lithography capabilities.
Implementation Method 1
forming an epitaxial layer of the first doping type on the substrate
Implementation Method 2
performing ion implantation on the etched epitaxial layer in sequence based on the second isolation dielectric layer
Data Source
AI summary
The present disclosure provides a trench field effect transistor structure and a manufacturing method thereof. The manufacturing method includes: providing a substrate (100), forming an epitaxial layer (101), forming a device trench (102) in the epitaxial layer, and forming a shielding dielectric layer (107), a shielding gate layer (105), a first isolation dielectric layer (108), a gate dielectric layer (109), a gate layer (110), a second isolation dielectric layer (112), a body region (114), a source (115), a source contact hole (118), a source electrode structure (122), and a drain electrode structure (123). During manufacturing of a trench field effect transistor structure, a self-alignment process is adopted in a manufacturing process, so that a cell pitch is not limited by an exposure capability and alignment accuracy of a lithography machine, to further reduce the cell pitch of the device, improve a cell density, and reduce a device channel resistance.