Trench-Gate MOSFET Spacer Alignment for Symmetric Body Doping
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Solution Overview
Problem
The challenge in manufacturing metal oxide semiconductor (MOS) transistors with reduced cell pitch is exacerbated by the need for precise photolithography alignment, which can lead to UIS performance degradation and asymmetrical doping distribution, complicating the integration of self-aligned contact methods in trench power MOSFET devices.
Innovation Solution
A method involving the formation of symmetrical spacers and recesses in the semiconductor body to auto-align source and body regions, allowing for dopant implantation and metal contact formation without the need for precise photolithography, thereby improving UIS performance and enabling reduced cell pitch without increasing manufacturing complexity or costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If photolithography alignment control is used to manufacture MOS transistors with reduced cell pitch, then device density increases, but alignment precision deteriorates leading to UIS performance degradation
Solution Approach 1:
The patent employs self-aligned fabrication techniques where the trench gate structure itself serves as the alignment reference for subsequent doping steps. The spacer regions are formed directly from the trench gate sidewalls, eliminating the need for separate photolithography alignment steps. This self-service approach ensures precise alignment while maintaining reduced cell pitch, resolving the contradiction between device density and alignment precision.
Solution Approach 2:
The patent performs preliminary formation of the trench gate structure and spacer regions before the actual doping steps. By pre-establishing the geometric framework through trench etching and spacer deposition, the subsequent dopant implantation is automatically aligned to the correct positions. This preliminary action eliminates alignment errors that would otherwise occur during photolithography steps.
2Ease of manufacture
If mask alignment is used for contact formation or enrichment, then manufacturing process is simplified, but doping distribution becomes asymmetrical leading to unbalanced current flow
Solution Approach 1:
The spacer regions automatically define the boundaries for dopant implantation and contact formation. The spacer width and position are determined by the trench gate dimensions, creating a self-aligning system that ensures symmetrical doping distribution. This eliminates the need for separate alignment masks while maintaining compositional symmetry, resolving the contradiction between manufacturing simplicity and doping distribution stability.
3Reliability
If body-well doping is increased to improve UIS capability, then UIS performance improves, but threshold voltage control becomes difficult
Solution Approach 1:
The patent applies different doping concentrations to different regions: high doping in the body-well region for UIS capability, and low doping in the channel region for threshold voltage control. The spacer structures enable precise spatial separation of these doping regions, allowing each zone to have optimized electrical properties. This local differentiation resolves the contradiction between UIS reliability and threshold voltage precision.
Solution Approach 2:
The patent changes the doping concentration parameter spatially across the device structure. By using the spacer-defined geometry to control dopant implantation depth and concentration, the body-well region receives high doping for UIS robustness while the channel maintains low doping for precise threshold voltage control. This parameter differentiation eliminates the trade-off between UIS capability and Vth precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances UIS capabilities by ensuring balanced current flow and reduced on-state resistance, allowing for logic-level threshold voltage control with lower body doping and enabling pitch reduction while maintaining high reliability and electrical insulation.
Implementation Method 1
implanting dopant species of the second type of conductivity in the first and the second recess using said first and second spacers as implant masks
Data Source
AI summary
A MOS transistor of vertical-conduction, trench-gate, type, including a first and a second spacer adjacent to portions of a gate oxide of the trench-gate protruding from a semiconductor substrate, the first and second spacers being specular to one another with respect to an axis of symmetry; enriched P+ regions are formed by implanting dopant species within the body regions using the spacers as implant masks. The formation of symmetrical spacers makes it possible to form source, body and body-enriched regions that are auto-aligned with the gate electrode, overcoming the limitations of MOS transistors of the known type in which such regions are formed by means of photolithographic techniques (with a consequent risk of asymmetry).