Trench Gate MOSFET Thick Oxide Reduces Parasitic Capacitance
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Solution Overview
Problem
Conventional trench MOSFETs suffer from increased delay time and decreased switching speed due to parasitic capacitance and leakage current caused by the thin first gate oxide film, which also lowers the breakdown voltage.
Innovation Solution
A trench MOSFET design where the thickness of the diffusion oxide film between the gate and the epi layer is selectively increased, reducing parasitic capacitance and enhancing the switching speed, while also increasing the breakdown voltage by forming a diffusion oxide film with a thickness of 1500 Å to 4000 Å, specifically 2000 Å to 2500 Å, and widening it beyond the trench width.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a thin first gate oxide film is used in the conventional trench MOSFET, then the device can be manufactured with simpler processes, but parasitic capacitance increases and switching speed decreases
Solution Approach 1:
The patent applies local quality by forming a thick diffusion oxide film specifically in the overlap region between the gate and epi layer, while maintaining a thin first gate oxide film elsewhere. This localized thickening reduces parasitic capacitance in the critical overlap region without unnecessarily increasing oxide thickness throughout the entire device, thus improving switching speed while maintaining manufacturing feasibility.
Solution Approach 2:
The patent introduces a vertical dimension solution by forming the thick diffusion oxide film at the bottom of the trench extending upwards, creating a three-dimensional oxide structure. This vertical arrangement effectively reduces the horizontal overlap area between gate and epi layer, thereby reducing parasitic capacitance without requiring changes to the basic planar device architecture.
2Device complexity
If a thin first gate oxide film is used, then the device structure remains simple, but leakage current increases and breakdown voltage decreases
Solution Approach 1:
The thick diffusion oxide film is formed locally in the overlap region where leakage current and high electric field occur most frequently. This localized reinforcement provides enhanced insulation and breakdown protection exactly where needed, preventing leakage current and increasing breakdown voltage without requiring the entire device structure to be more complex.
Solution Approach 2:
The thick diffusion oxide film is formed in advance during the manufacturing process to prevent leakage current and breakdown before they can occur during device operation. By proactively addressing the potential failure mechanism in the overlap region with a pre-formed thick oxide barrier, the patent prevents reliability issues rather than attempting to correct them after they manifest.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The increased diffusion oxide film thickness reduces parasitic capacitance, improves switching speed, and increases the breakdown voltage, thereby enhancing the overall performance of the trench MOSFET.
Implementation Method 1
subjecting the etched epi layer to thermal oxidation, thus forming a diffusion oxide film
Data Source
AI summary
A trench MOSFET including a substrate (100) having an epi layer (110) and a body layer (120) sequentially formed thereon, a trench (131) formed vertically in the central portion of the epi layer and the body layer, a first gate oxide film (132) formed on the inner wall of the trench, a trench bottom oxide film (135) formed by thermal oxidation in the epi layer between the lower surface of the trench and the upper surface of the substrate to have a thickness greater than a thickness of the first gate oxide film and a width greater than a width of the trench, a gate (130) formed in the trench having the first gate oxide film, a second gate oxide film (160) formed on the gate, and a source region (140) formed at both sides of the upper portion of the gate. The trench bottom oxide film reduces the generation of parasitic capacitance between the epi layer corresponding to a drain region and the gate, thereby improving a switching speed.