Trench Oxide Semiconductor Memory Cells for Buried Word Line Performance
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Solution Overview
Problem
Current memory devices face challenges in improving operation performance, particularly in three-dimensional structures with buried word lines and stacked capacitors, where existing designs and manufacturing processes fall short in enhancing performance effectively.
Innovation Solution
A memory device is designed with an oxide semiconductor layer disposed in trenches, accompanied by a gate dielectric layer and word line structures, which are formed on the substrate with active regions and an isolation structure, to enhance operational performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If three-dimensional memory cell structures with buried word lines and stacked capacitors are used, then memory cell size is reduced, but operation performance deteriorates
Solution Approach 1:
The patent introduces a new dimensional approach by forming oxide semiconductor layers in trenches extending from the surface into the substrate, creating a vertical channel structure that adds a depth dimension to the conventional planar transistor layout. This enables improved performance within the same footprint by utilizing the third dimension for charge transport
Solution Approach 2:
The patent employs composite material structures by combining oxide semiconductor layers with high-k gate dielectric materials and metal gate electrodes. This composite approach allows simultaneous optimization of carrier mobility (through oxide semiconductor) and gate control (through high-k dielectric), resolving the performance limitation in scaled three-dimensional structures
2Ease of manufacture
If conventional semiconductor materials and structures are used, then manufacturing process is simpler, but operation performance and energy efficiency deteriorate
Solution Approach 1:
The patent changes the material parameter from conventional silicon-based semiconductors to oxide semiconductors, which exhibit superior carrier mobility and lower off-state current. This material parameter change enables improved on-current and off-current characteristics while maintaining compatibility with existing semiconductor manufacturing processes through appropriate deposition and annealing techniques
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The configuration of the oxide semiconductor layer in trenches increases the overlap area with word line structures, leading to improved transistor performance, increased on-current, reduced off-current, faster write recovery time, and optimized operational power consumption.
Implementation Method 1
Incorporating an oxide semiconductor layer disposed in trenches with conformal deposition to enhance the memory device's performance
Data Source
AI summary
A memory device and a manufacturing method thereof are disclosed in the present invention. The memory device includes a substrate, trenches, an oxide semiconductor layer, a gate dielectric layer, and word line structures. The substrate includes active regions and an isolation structure located between the active regions. The active regions contain silicon. The trenches are disposed in the active regions and the isolation structure. The oxide semiconductor layer is disposed in each trench. The gate dielectric layer is disposed on the oxide semiconductor layer and located in each trench. The word line structures are disposed on the gate dielectric layer and located in the trenches, respectively. At least a portion of the gate dielectric layer is disposed between the oxide semiconductor layer and each word line structure.