Trench and Planar MOSFET Integration With Segmented Substrate Processing
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Solution Overview
Problem
The manufacturing process of trench gate type MOSFETs and planar type MOSFETs on the same semiconductor substrate is complex, leading to defects and reduced reliability and yield due to differing device configurations and required properties.
Innovation Solution
A method of manufacturing a semiconductor device that involves forming MOSFETs with distinct regions, including trench and planar types, by creating specific conductivity types, gate insulating films, and source/drain regions, followed by interlayer insulating films and plug formation, to improve integration and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If trench gate type MOSFET and planar type MOSFET are formed in the same semiconductor substrate, then integration and miniaturization are achieved, but manufacturing process complexity increases and reliability decreases
Solution Approach 1:
The patent divides the semiconductor substrate into distinct first and second regions, each dedicated to specific MOSFET types. The manufacturing process is segmented into separate sequences for trench gate MOSFETs (forming trenches, gate insulating films, and gate electrodes in the first region) and planar MOSFETs (forming well regions and gate structures in the second region). This segmentation allows each MOSFET type to be manufactured using its optimized process while coexisting on the same substrate, thus reducing overall manufacturing complexity despite the integrated design.
Solution Approach 2:
The patent applies different manufacturing approaches to different regions of the substrate. The first region uses trench gate structure formation with specific gate insulating films and gate electrodes, while the second region uses planar MOSFET formation with well regions. Each region is treated with locally optimized processes suited to its specific MOSFET type requirements, enabling high-quality fabrication of both types without forcing a uniform approach that would compromise either.
2Area of stationary object
If trench gate type MOSFET and planar type MOSFET are formed in the same semiconductor substrate, then integration is achieved, but yield decreases due to manufacturing defects
Solution Approach 1:
By segregating the substrate into first and second regions with dedicated manufacturing sequences for each MOSFET type, the patent prevents process conflicts that would generate defects. The trench gate MOSFET process (involving trench formation, gate insulating film deposition, and gate electrode formation) is executed separately from the planar MOSFET process (involving well region formation and gate structure creation), eliminating cross-contamination and process interference that would otherwise reduce yield.
Solution Approach 2:
The patent performs preliminary region-specific preparations before forming the respective MOSFET structures. The first region is prepared with appropriate doping and trench formation prior to gate insulating film formation, while the second region undergoes well region formation and doping in advance. These preliminary actions ensure that each region is optimally prepared for its specific MOSFET type fabrication, preventing defects that would arise from improper substrate preparation.
Data Source
AI summary
In a semiconductor substrate SUB, a trench TR is formed.A gate-electrode GE1 is formed inside the trench TR via a gate insulating film GI1. A body region PB, a well region PW1 and a well region NW1 are formed. A source-region NS is formed in the body-region PB. In the well region PW1, an n-type source region and an n-type drain region are formed. In the well region NW1, a p-type source region and a p-type drain region are formed. An interlayer insulating film IL1 is formed on the upper surface of semiconductor substrate SUB. In the interlayer insulating film IL1, a hole CH1 is formed in the source region NS and in the body region PB. Holes CH3 are formed in the interlayer insulating film IL1 so as to reach the n-type source region, the n-type drain region, the p-type source region and the p-type drain region.