Integrated Trench and Planar MOSFET Layout for Yield Reliability
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Solution Overview
Problem
The manufacturing process of trench gate type MOSFETs and planar type MOSFETs on the same semiconductor substrate is complex, leading to defects and reduced reliability and yield due to differing device configurations and properties.
Innovation Solution
A method of manufacturing a semiconductor device with separate regions for each type of MOSFET, including forming trench structures, gate insulating films, and gate electrodes, along with specific well regions and source/drain regions, and performing heat treatments to improve reliability and yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If trench gate type MOSFET and planar type MOSFET are formed in the same semiconductor substrate, then mounting cost is reduced and device size is miniaturized, but manufacturing process complexity increases and reliability decreases
Solution Approach 1:
The semiconductor substrate is divided into a first region for trench gate type MOSFETs and a second region for planar type MOSFETs. This spatial segmentation allows each MOSFET type to be manufactured using its own optimized process steps independently, avoiding the complexity that would arise from trying to manufacture both types using a single unified process.
Solution Approach 2:
Different regions of the semiconductor substrate are assigned different device configurations and manufacturing processes according to their specific requirements. The first region receives trench gate formation processes while the second region receives planar gate formation processes, allowing each region to have the local quality (device structure and process) best suited for its intended function.
2Adaptability or versatility
If trench gate type MOSFET and planar type MOSFET are formed in the same semiconductor substrate, then integration is achieved, but manufacturing defects increase and yield decreases
Solution Approach 1:
By segmenting the substrate into distinct first and second regions, each dedicated to a specific MOSFET type, the manufacturing process can be optimized for each device type independently. This reduces the risk of manufacturing defects that would arise from attempting to accommodate both device types in a single uniform process flow.
Solution Approach 2:
The patent establishes region-specific manufacturing processes in advance, where the first region is prepared for trench gate formation and the second region is prepared for planar gate formation before actual device fabrication begins. This preliminary differentiation of manufacturing approaches prevents cross-contamination of process steps and reduces manufacturing defects.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the reliability of semiconductor devices and suppresses yield decreases by simplifying the manufacturing process and optimizing the integration of trench gate and planar type MOSFETs on the same substrate.
Implementation Method 1
performing a second heat treatment on the first source region, the second source region, the second drain region, the third source region, and the third drain region
Data Source
AI summary
Reliability of a semiconductor device is improved and reduction in yield is reduced. In a semiconductor substrate SUB, a trench TR is formed. A gate-electrode GE1 is formed inside the trench TR via a gate insulating film GI1. In the semiconductor substrate SUB, a body region PB, a well region PW1 and a well region NW1 are formed. A source-region NS is formed in the body-region PB. In the well region PW1, an n-type source region and an n-type drain region are formed. In the well region NW1, a p-type source region and a p-type drain region are formed. The source region NS, the n-type source region, the n-type drain region, the p-type source region and the p-type drain region are subjected to heat treatment. After heat treatment, a p-type column region PC is formed in the semiconductor substrate SUB located below the body region PB.