Trench Plug Hardmask Structure for 10 nm Fin Contact Scaling
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Solution Overview
Problem
Current fabrication processes for integrated circuits face challenges in scaling to the 10 nanometer node or smaller, due to variability in conventional processes, which limits the extension of existing methodologies.
Innovation Solution
The implementation of a pitch quartering approach for patterning semiconductor layers to form semiconductor fins, along with the use of merged fin pitch quartering and fin trim isolation techniques, to enhance the fabrication of advanced integrated circuit structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional fabrication processes are used for scaling, then existing methodologies can be maintained, but manufacturing precision deteriorates at 10 nanometer node or smaller
Solution Approach 1:
The patent applies pitch quartering methodology that divides the patterning process into multiple stages: first forming mandrels at relaxed pitch, then creating spacers around mandrels, removing mandrels, and repeating the process to achieve quartered pitch. This segmentation transforms a single high-precision step into multiple lower-precision steps, each operating at relaxed dimensions while collectively achieving ultra-fine 10nm or smaller features with controlled variability
Solution Approach 2:
The methodology performs preliminary actions by first forming mandrels at larger dimensions where conventional lithography maintains good precision, then using these mandrels as templates for subsequent spacer formation. This preliminary structuring at relaxed pitch establishes a foundation that guides the creation of finer features, ensuring that each subsequent step operates from a controlled, pre-defined geometry that reduces variability
2Productivity
If feature size is reduced to increase device density, then transistor density improves, but manufacturing precision deteriorates
Solution Approach 1:
The patent transitions from two-dimensional lithographic patterning to three-dimensional spacer-based patterning. By forming vertical spacers around horizontal mandrels, the methodology uses the vertical dimension to define horizontal feature dimensions. This dimensional transformation allows the critical horizontal pitch to be determined by vertical spacer thickness (controlled by conformal deposition) rather than by lithographic resolution, thereby decoupling feature size control from optical diffraction limits and enabling higher transistor density with maintained precision
Solution Approach 2:
The patent introduces mandrels as intermediary structures that serve as temporary templates for spacer formation. These mandrels are formed at relaxed pitch using conventional lithography, then act as guides for depositing spacers that define the final fine-pitch features. The mandrels mediate between the capabilities of conventional lithography and the requirements for ultra-fine pitch, allowing high transistor density to be achieved while maintaining manufacturing precision through the intermediary's controlled geometry
Data Source
AI summary
Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin comprising silicon. A plurality of gate structures is over the fin, individual ones of the plurality of gate structures along a direction orthogonal to the fin and having a pair of dielectric sidewall spacers. A trench contact structure is over the fin and directly between the dielectric sidewalls spacers of a first pair of the plurality of gate structures. A contact plug is over the fin and directly between the dielectric sidewalls spacers of a second pair of the plurality of gate structures, the contact plug comprising a lower dielectric material and an upper hardmask material.