Trench Polysilicon Semiconductor Structure for Lower Rdson

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Solution Overview

Problem

Existing semiconductor devices face challenges in reducing the drain-source on-resistance (Rdson) due to fixed drain side substrate spreading resistance, which increases the total Rdson, especially for low breakdown voltage classes.

Innovation Solution

A semiconductor device structure is proposed with a silicon substrate, a channel, and a drift region, featuring multiple polysilicon layers isolated by gate and RESURF oxides, which creates a bi-directional current path that skips substrate spreading resistance, allowing for reduced Rdson by using one bi-directional switch instead of two unidirectional switches in series.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If drain side substrate spreading resistance is reduced by backside metallization and deep implants, then bidirectional resistance and drain side EPI spreading resistance are reduced, but device complexity and manufacturing difficulty increase

Engineering Contradiction:
Improvebidirectional resistanceVSAvoiddevice complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent extracts the substrate spreading resistance problem from the conventional current path by creating a trench that separates the drain region from the substrate. This extraction eliminates the need for backside metallization and deep implants to reduce spreading resistance, as the trench itself provides the isolation and current path optimization.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent introduces a vertical dimension by creating a trench structure that extends into the substrate. This dimensional change allows the current to flow through a dedicated path in the vertical dimension, bypassing the lateral substrate spreading resistance that would otherwise affect horizontal current flow.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Reliability

If drain side substrate spreading resistance is reduced by backside metallization and deep implants, then drain side EPI spreading resistance is reduced, but manufacturing precision requirements increase

Engineering Contradiction:
Improvedrain side EPI spreading resistanceVSAvoidmanufacturing precision
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent extracts the EPI spreading resistance issue from the conventional structure by creating a trench that isolates the drain region. This extraction provides a dedicated current path that reduces EPI spreading resistance without requiring precise control of deep implant parameters or complex backside metallization processes.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The trench acts as an intermediary structure between the drain region and the substrate. It provides a controlled interface that manages the current flow and reduces spreading resistance without requiring high-precision manufacturing of the substrate or EPI layer themselves.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentEP4333074A1A semiconductor device and a method of manufacturing of a semiconductor device
Publication Date: 2024.03.06 NEXPERIA BV
  • EP4333074A1 patent drawingFigure 1~2
  • EP4333074A1 patent drawingFigure 3
  • EP4333074A1 patent drawing

AI summary

The present disclosure proposes a semiconductor device comprising a silicon substrate; a channel positioned on the top surface of the substrate; a drift region positioned on the top of the channel; a trench; a first polysilicon layer positioned within the channel and the drift region on the bottom of the trench; a second polysilicon layer positioned on the top of the first polysilicon layer, and positioned within the drift region inside of the trench; a third polysilicon layer positioned on the top of the second polysilicon layer, and positioned within the drift region inside of the trench; wherein the first polysilicon layer and the second polysilicon layer and the third polysilicon layer are isolated by a gate oxide and a RESURF oxide respectively, from the channel and from the drift and from each other forming at least partially three separated structures.