Trench Bottom Polysilicon for Power Semiconductor Capacitance Reduction

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Solution Overview

Problem

Existing power semiconductor devices face challenges in reducing input capacitance and reverse transfer capacitance, which contribute to switching loss, particularly under high-frequency applications, and current fabrication methods are complex and costly.

Innovation Solution

A power semiconductor device with a trench-based design featuring a heavily doped polysilicon structure and a gate dielectric layer, where dopants are driven to form a heavily doped region, reducing capacitance through a thermal drive-in step and optimized trench formation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of energy

If conventional fabrication methods are used to reduce input capacitance and reverse transfer capacitance, then switching loss is reduced, but fabrication process becomes complicated and cost increases

Engineering Contradiction:
Improveswitching lossVSAvoidfabrication process complexity
Core Design Contradiction:
Loss of energyVSDevice complexity

Solution Approach 1:

The patent changes the doping concentration parameter by forming a heavily doped polysilicon region at the trench bottom with high doping concentration (e.g., 1E19 to 1E21 atoms/cm³), which modifies the electric field distribution and reduces capacitance values without requiring complex fabrication processes

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent performs preliminary doping action by forming the heavily doped polysilicon region at the trench bottom before final device completion. This preliminary doping establishes the desired capacitance characteristics early in the process, simplifying subsequent fabrication steps

Inventive Principle:
Principle #10Preliminary action

2Area of moving object

If trench-based structure is implemented to reduce unit cell size, then cell integration is enhanced, but fabrication process becomes more complex

Engineering Contradiction:
Improveunit cell sizeVSAvoidfabrication process complexity
Core Design Contradiction:
Area of moving objectVSDevice complexity

Solution Approach 1:

The patent merges the trench isolation structure with the gate electrode formation into a single integrated structure. The gate electrode is formed within the trench, combining what would traditionally be separate isolation and gating elements into one unified fabrication sequence, thereby reducing process complexity while maintaining compact unit cell dimensions

Inventive Principle:
Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution effectively reduces input capacitance and reverse transfer capacitance, enhancing switching speed and minimizing switching loss while simplifying the fabrication process.

Implementation Method 1

The dopants in the heavily doped polysilicon structure are driven through at least the side surface thereof to form a heavily doped region in the base

Methodology Applied
Scientific EffectThermal diffusion: Diffusion

Implementation Method 2

applying a thermal drive-in step to diffuse dopants in the heavily doped polysilicon structure

Methodology Applied
Scientific EffectThermal heating: Heating

Data Source

PatentUS8445958B2Power semiconductor device with trench bottom polysilicon and fabrication method thereof
Publication Date: 2013.05.21 SUPER GRP SEMICON CO LTD
  • US8445958B2 patent drawing
  • US8445958B2 patent drawing
  • US8445958B2 patent drawing

AI summary

A power semiconductor device comprising a base, a trench, a heavily doped polysilicon structure, a polysilicon gate, a gate dielectric layer, and a heavily doped region is provided. The trench is formed in the base. The heavily doped polysilicon structure is formed in the lower portion of the trench. At least a side surface of the heavily doped polysilicon structure touches the naked base. The polysilicon gate is located in the upper portion of the trench. The gate dielectric layer is interposed between the polysilicon gate and the heavily doped polysilicon structure. The dopants in the heavily doped polysilicon structure are diffused outward to form a heavily doped region.