Trench Schottky Rectifier Layout for Lower Cathode Resistance
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Solution Overview
Problem
Conventional Schottky rectifiers face challenges with high epi-resistivity and cathode contact resistance, leading to forward voltage margin issues and low yield, particularly in Chip-Scale Package (CSP) applications, due to high substrate thickness and process fluctuations.
Innovation Solution
The development of a semiconductor Schottky rectifier with a trench structure cathode and anode configuration, where the cathode trench has vertical sidewalls and a horizontal extension, covered with a gate oxide film, and a polysilicon element separated by an interlayer dielectric or metal silicide, allowing for improved current handling and reduced parasitic resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional planar Schottky CSP device structure is used, then manufacturing is simpler, but forward voltage margin is poor and yield is low due to high epi-resistivity and cathode contact resistance
Solution Approach 1:
The cathode structure is segmented into multiple components: a cathode trench extending into the epi-layer, a cathode contact region at the bottom, and a cathode electrode on the surface. This segmentation allows separate optimization of contact resistance (at the trench bottom) and surface connectivity (at the electrode), improving overall cathode performance and forward voltage margin without requiring complex multi-layer structures.
Solution Approach 2:
The invention transitions from a conventional planar two-dimensional cathode layout to a three-dimensional trench structure. The cathode trench provides a vertical pathway through the epi-layer, enabling current to flow directly from the surface electrode to the substrate contact region, thereby reducing the effective current path length and contact resistance while maintaining simple planar processing steps.
2Reliability
If substrate thickness is reduced to 50 um for better Vf, then wafer to wafer bonding and backside processing is required, but manufacturing cost increases
Solution Approach 1:
The cathode trench is formed extending into the epi-layer before final device assembly, pre-positioning the current path and contact regions. This preliminary structuring allows the device to achieve low forward voltage with the original substrate thickness, eliminating the need for costly post-manufacturing wafer bonding and backside thinning processes.
3Reliability
If POCl3 doped area density is increased to improve contact, then process fluctuation increases causing Vf spreading and yield problems
Solution Approach 1:
The invention extracts the cathode contact function from the POCl3 doped area by creating a separate cathode trench that extends to the substrate or deep into the epi-layer. The trench bottom serves as the primary contact region, while the POCl3 doped area provides only secondary support, thereby reducing the impact of doping density fluctuations on overall contact quality and Vf uniformity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables Schottky rectifiers to operate at higher currents with improved forward voltage and leakage current characteristics, addressing the yield and dimensionality issues of conventional Schottky CSP devices.
Implementation Method 1
The surfaces of the sidewall and the bottom extension are covered with a gate oxide film. The gate oxide film separates the epi-layer from a polysilicon element.
Implementation Method 2
depositing a first metal layer and performing a thermal treatment to form metal silicide in the Schottky diode region and the cathode region
Implementation Method 3
performing a thermal treatment to form metal silicide
Implementation Method 4
a Schottky contact disposed between a second silicide layer and the epi-layer
Data Source
AI summary
A method for forming a semiconductor Schottky rectifier device includes providing a semiconductor substrate, forming a hard mask for trench etch including openings for guard rings, an anode region, and a cathode region, and etching semiconductor epitaxial material layer to form a plurality of trenches. The method also includes forming a first dielectric layer and depositing a polysilicon layer, performing an anisotropic etch of the polysilicon layer to form polysilicon elements on sidewalls of the trench, and depositing and etching a second dielectric layer to expose a Schottky diode region and a bottom region of the trench in the cathode region. The method further includes depositing a first metal layer and performing a thermal treatment to form metal silicide in the Schottky diode region and the cathode region and forming a second metal layer and separating the second metal layer into an anode electrode and a cathode electrode.