Trench Semiconductor Structure for Low On-Resistance and High Breakdown

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Solution Overview

Problem

There is a trade-off relationship between on-resistance and breakdown voltage in semiconductor devices with p-type and n-type layers, where improving one characteristic often deteriorates the other.

Innovation Solution

The semiconductor device incorporates a trench structure with a gate insulating film and a gate electrode, along with p-type deep layers, n-type deep layers, and an n-type high concentration layer. The n-type high concentration layer is in contact with the lower surface of the p-type deep layers, restricting the spread of depletion layers and securing a wide current path, thereby achieving low on-resistance and high breakdown voltage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of energy

If p-type and n-type layers are repeatedly arranged to reduce on-resistance, then on-resistance decreases, but breakdown voltage deteriorates

Engineering Contradiction:
Improveon-resistanceVSAvoidbreakdown voltage
Core Design Contradiction:
Loss of energyVSReliability

Solution Approach 1:

The device segments the current path into multiple parallel channels by arranging multiple p-type deep layers and n-type deep layers alternately. This segmentation allows the current to flow through multiple paths, reducing the overall on-resistance while maintaining adequate breakdown voltage through the alternating structure that prevents depletion layer merger.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies local quality by creating regions with different impurity concentrations and types. The p-type deep layers have high p-type impurity concentration, while the n-type deep layers have high n-type impurity concentration, and the drift layer has lower n-type impurity concentration. This local differentiation optimizes both conduction in the on-state and depletion characteristics in the off-state, resolving the trade-off between on-resistance and breakdown voltage.

Inventive Principle:
Principle #3Local quality

2Loss of energy

If deep layers are added to reduce on-resistance, then on-resistance decreases, but device complexity increases

Engineering Contradiction:
Improveon-resistanceVSAvoidlayer structure
Core Design Contradiction:
Loss of energyVSDevice complexity

Solution Approach 1:

The patent merges multiple functions into the deep layer structure. The alternating p-type and n-type deep layers simultaneously serve as conduction paths for reducing on-resistance and as depletion regions for maintaining breakdown voltage. This merging of functions reduces the need for separate structural elements, thereby limiting the increase in device complexity while achieving low on-resistance.

Inventive Principle:
Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The semiconductor device achieves both low on-resistance and high breakdown voltage by restricting the spread of depletion layers through the n-type high concentration layer, effectively addressing the trade-off relationship between these characteristics.

Implementation Method 1

an n-type high concentration layer being in contact with at least a part of a lower surface of a corresponding p-type deep layer in the plurality of p-type deep layers and having a higher concentration of n-type impurities than the drift layer

Methodology Applied
Scientific EffectDepletion layer spread restriction:

Implementation Method 2

a gate insulating film covering an inner surface of the trench, and a gate electrode located in the trench and insulated from the semiconductor substrate by the gate insulating film

Methodology Applied
Scientific EffectElectrical insulation: Dielectric

Data Source

PatentUS20250040205A1Semiconductor device and manufacturing method of semiconductor device
Publication Date: 2025.01.30 DENSO CORP
  • US20250040205A1 patent drawing
  • US20250040205A1 patent drawing
  • US20250040205A1 patent drawing

AI summary

A semiconductor device includes a plurality of p-type deep layers, a plurality of n-type deep layers, a drift layer of n-type, and an n-type high concentration layer. The n-type high concentration layer is in contact with at least a part of a lower surface of a corresponding p-type deep layer in the plurality of p-type deep layers and has a higher concentration of n-type impurities than the drift layer.