Trench Semiconductor Capacitance Stabilization

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Solution Overview

Problem

Conventional semiconductor devices experience significant fluctuations in output capacitance and feedback capacitance when the collector-emitter voltage is increased, leading to electromagnetic noise and potential malfunctions.

Innovation Solution

A semiconductor device design featuring a first impurity region, a second impurity region, and groove portions with specific insulating films and electrodes, along with a gate wiring system, an interlayer insulating film, and an electric charge storage layer with controlled impurity concentrations and widths to stabilize capacitance and reduce noise.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional semiconductor device structures are used, then device functionality is maintained, but output capacitance and feedback capacitance fluctuate significantly when collector-emitter voltage is increased, leading to electromagnetic noise

Engineering Contradiction:
Improvecapacitance stabilityVSAvoidelectromagnetic noise
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The base region is divided into multiple impurity regions with different conductivity types and concentration levels. Specifically, a first impurity region (n-type, low concentration) is formed between the collector electrode and base region, while a second impurity region (p-type, high concentration) is formed at the base region surface. This segmentation creates distinct functional zones that stabilize capacitance characteristics by controlling charge distribution under varying voltage conditions.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different regions of the base are assigned different impurity concentrations and conductivity types to optimize local electrical characteristics. The first impurity region has low impurity concentration to reduce capacitance fluctuation, while the second impurity region has high impurity concentration to maintain conductivity. Groove portions with insulating films are selectively formed in certain regions to further control electric field distribution and stabilize capacitance.

Inventive Principle:
Principle #3Local quality

2Power

If impurity concentration in the base region is increased to improve conductivity, then on-voltage decreases, but capacitance fluctuation increases when voltage changes

Engineering Contradiction:
Improveon-voltageVSAvoidcapacitance stability
Core Design Contradiction:
PowerVSReliability

Solution Approach 1:

The invention employs a multi-layer impurity structure with varying parameters. The first impurity region uses low impurity concentration (1×10^16 to 1×10^18 atoms/cm³) to stabilize capacitance, while the second impurity region uses high impurity concentration (1×10^18 to 1×10^20 atoms/cm³) to maintain low on-voltage. This parameter differentiation across regions allows simultaneous optimization of both conductivity and capacitance stability.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The design effectively suppresses fluctuations in output and feedback capacitance, thereby minimizing electromagnetic noise and ensuring stable device operation even under varying voltage conditions.

Implementation Method 1

a gate insulating film interposed therebetween; an interlayer insulating film formed on the first electrode and capable of insulating the main electrode and the first electrode from each other

Methodology Applied
Scientific EffectElectrical insulation: Dielectric

Data Source

PatentUS8178947B2Semiconductor device
Publication Date: 2012.05.15 MITSUBISHI ELECTRIC CORP
  • US8178947B2 patent drawing
  • US8178947B2 patent drawing
  • US8178947B2 patent drawing

AI summary

There is provided a semiconductor device in which an amount of fluctuations in output capacitance and feedback capacitance is reduced. In a trench-type insulated gate semiconductor device, a width of a portion of an electric charge storage layer in a direction along which a gate electrode and a dummy gate are aligned is set to be at most 1.4 μm.