Trench Semiconductor Layout for Lower Forward Voltage Drop
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Solution Overview
Problem
Current semiconductor devices face challenges in reducing forward voltage drop and reverse current while maintaining efficient electrical characteristics, particularly due to limitations in the design of trenches and well regions which affect the formation of depletion and inversion layers.
Innovation Solution
The semiconductor device incorporates a specific configuration with n-type trenches, insulation layers, embedded electrodes, and a p-type well region in the inter-trench region, where the well region has varying p-type impurity concentrations and dimensions to enhance the formation of depletion and inversion layers, reducing electrical resistivity and forward voltage drop.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional trench and well region designs are used, then device structure is simple, but forward voltage drop is high and reverse current is high
Solution Approach 1:
The patent applies local quality by creating distinct regions with different impurity concentrations within the well region. Specifically, it forms a first well region with a first impurity concentration and a second well region with a second impurity concentration that is higher than the first. This localized variation in impurity concentration optimizes the electrical characteristics in different areas, reducing forward voltage drop and reverse current while maintaining overall device functionality.
Solution Approach 2:
The patent segments the well region into multiple distinct regions (first well region and second well region) with different impurity concentrations. It also segments the trench structure into multiple trenches arranged in a specific pattern. This segmentation allows each region to perform its specific function optimally, contributing to reduced forward voltage drop and reverse current through the collective effect of the segmented structure.
2Reliability
If trench depth and well region dimensions are increased, then depletion and inversion layer formation is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies parameter changes by systematically varying the impurity concentration parameter across different well regions. The first well region has a first impurity concentration while the second well region has a higher second impurity concentration. This parameter variation allows the device to achieve reliable depletion and inversion layer formation without requiring excessive trench depth or well region dimensions, thereby balancing reliability with manufacturability.
3Loss of energy
If impurity concentration in well region is increased, then electrical resistivity decreases, but reverse current increases
Solution Approach 1:
The patent resolves this contradiction by applying local quality through spatially differentiated impurity concentrations. The first well region maintains a lower impurity concentration to minimize reverse current, while the second well region has a higher impurity concentration to reduce electrical resistivity. This localized optimization allows the device to achieve low resistivity in critical areas without suffering from high reverse current throughout the entire structure.
Solution Approach 2:
The patent segments the well region into multiple regions with different impurity concentrations, allowing each segment to contribute differently to the overall electrical characteristics. The first well region segment focuses on minimizing reverse current, while the second well region segment focuses on reducing electrical resistivity. The combined effect of these segmented regions achieves both low resistivity and controlled reverse current.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces the forward voltage drop and reverse current by increasing electric field intensity in the inter-trench region, improving the electrical characteristics of the semiconductor device.
Implementation Method 1
enhance the formation of depletion and inversion layers
Implementation Method 2
enhance the formation of depletion and inversion layers
Implementation Method 3
reducing electrical resistivity and forward voltage drop
Implementation Method 4
increasing electric field intensity in the inter-trench region
Implementation Method 5
reducing electrical resistivity and forward voltage drop
Data Source
AI summary
This semiconductor device comprises a semiconductor substrate of a first conductivity type, a semiconductor layer of the first conductivity type, a first electrode, a second electrode, a first trench, a second trench, an insulating layer, a third electrode, and a well region of a second conductivity type. The well region includes a first region that is adjacent to the first trench, a second region that is adjacent to the second trench, and a third region that is located between the first region and the second region in a second direction. The impurity concentration of the first region and the impurity concentration of the second region are both lower than the impurity concentration of the third region.