Trench Semiconductor Device Self-Aligned Contact Trench
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Trench type semiconductor devices face challenges in achieving minute structures, reducing on resistance, and improving breakdown capability due to difficulties in forming thick interlayer insulating films and securing contact areas, especially with the miniaturization of device structures.
Innovation Solution
A trench type semiconductor device with a self-aligned structure, featuring a high resistivity first base layer, gate insulating film, gate electrode, interlayer insulating film, and second base layer, where the interlayer insulating film is formed with a higher impurity concentration than the semiconductor region, allowing for thicker film formation and improved insulation, and a self-aligned contact trench is used to increase the contact area and reduce on resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the interlayer insulating film is made thicker to improve insulation, then breakdown capability is improved, but device structure cannot be miniaturized and on resistance increases
Solution Approach 1:
The patent applies local quality by forming the interlayer insulating film with a higher impurity concentration specifically in the region covering the gate electrode, while maintaining lower impurity concentration in other semiconductor regions. This localized high impurity concentration increases the film's volume capacity and insulation performance in the critical area without requiring the entire device structure to be scaled up, thus resolving the contradiction between breakdown capability and device miniaturization.
2Productivity
If the contact area is reduced to achieve device miniaturization, then integration density improves, but on resistance and contact resistance increase
Solution Approach 1:
The patent resolves the contact area contradiction by transitioning from a planar contact structure to a three-dimensional self-aligned contact trench structure. The contact trench extends vertically into the semiconductor substrate, providing additional contact area through the sidewalls while maintaining a compact planar footprint. This dimensional change allows integration density to improve without sacrificing contact area, thus reducing on resistance.
3Length of stationary object
If high temperature or long duration heat treatment is applied to form thick local oxidation film, then insulation thickness is sufficient, but element characteristics of the MOS transistor are degraded
Solution Approach 1:
The patent applies parameter changes by modifying the impurity concentration parameter of the interlayer insulating film rather than relying solely on thermal parameters (temperature and duration). By introducing a higher impurity concentration in the interlayer insulating film, the volume capacity and insulation performance are enhanced without requiring extreme heat treatment conditions that would degrade the MOS transistor's element characteristics.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables the achievement of minute structures with reduced on resistance and improved breakdown capability by increasing the interlayer insulating film's volume capacity and forming a thicker, more effective insulating film, while also enhancing contact area and reducing contact resistance.
Implementation Method 1
the interlayer insulating film is formed with a higher impurity concentration than the semiconductor region, allowing for thicker film formation and improved insulation
Implementation Method 2
Ion implantation is performed to the interlayer insulating film (310) formed by the self-alignment by the LOCOS, and the impurity concentration of the interlayer insulating film (310) is made larger than the impurity concentration of the regions (12, 13) formed in the substrate (2)
Data Source
AI summary
A fabrication method for a trench type semiconductor device includes: forming a first base layer; forming a gate insulating film on a bottom and sidewall surfaces of a trench; forming a gate electrode for filling up into the trench; covering the gate electrode and forming an interlayer insulating film; forming a second base layer on the first base layer; forming a first main electrode layer on the second base layer; forming a first main electrode which passes through the first main electrode layer by applying the interlayer insulating film as a mask, is connected to the second base layer in the bottom surface of a self-aligned contact trench, and is connected to the first main electrode layer of the self-aligned contact trench; forming a second main electrode layer at a back side of the first base layer; and forming a second main electrode at the second main electrode layer.