Trench-Shaped Opening in Semiconductor Package Mold Layer
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Solution Overview
Problem
The production of multi-chip stack packages in the semiconductor industry faces yield reduction and packaging inefficiencies, particularly in achieving high-density chip stacks with reliable electrical connections, due to the limitations of conventional package-on-package (POP) technologies.
Innovation Solution
A semiconductor package design featuring a lower package with a trench-shaped opening in the mold layer to expose connection terminals, allowing for efficient electrical connection with an upper package through a reflow process, which enhances mechanical and electrical characteristics by preventing gas pressure buildup and maintaining a gap between the packages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional package-on-package (POP) technology is used to achieve high-density chip stacks, then integration density is improved, but production yield is reduced
Solution Approach 1:
The patent divides the connection terminal structure into multiple functional zones: a first region with connection terminals exposed through the mold layer for electrical connection, and a second region with the mold layer intact for structural support and protection. This segmentation allows different areas to serve different functions, enabling high-density integration while maintaining reliable connections and improving production yield through standardized manufacturing processes.
2Reliability
If connection terminals are exposed through the mold layer to enable electrical connection, then electrical connectivity is improved, but mechanical strength is reduced
Solution Approach 1:
The patent applies local quality by creating a first region where the mold layer is removed to expose connection terminals for electrical connectivity, while maintaining the mold layer in a second region to provide mechanical strength. This localized modification allows the structure to have different properties in different areas: electrical connectivity where needed and structural support where required, resolving the contradiction between exposure for connection and coverage for strength.
3Strength
If the mold layer completely covers the package substrate for protection, then mechanical protection is improved, but electrical connection reliability is reduced
Solution Approach 1:
The patent segments the mold layer coverage into a first region without mold layer to expose connection terminals for reliable electrical connection, and a second region with complete mold layer coverage for mechanical protection. This selective segmentation enables both functions to coexist: the exposed terminals in the first region ensure electrical connection reliability, while the covered area in the second region provides mechanical protection.
4Quantity of substance
If multiple connection terminals are densely arranged to achieve high-density stacking, then integration capacity is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies preliminary action by forming the connection terminals and their supporting structures (such as the first and second supporting structures) before final assembly. The mold layer is selectively removed after terminal formation but before packaging completion, allowing terminals to be precisely positioned and connected while the mold layer remains intact during manufacturing to provide structural guidance and protection, thereby reducing precision requirements during critical assembly steps.
Data Source
AI summary
Provided are semiconductor packages and methods of fabricating the same. In one embodiment, the package may include an upper package stacked on a lower package, and a plurality of connection terminals electrically connecting the lower and upper packages. The lower package may include a lower package substrate, a lower semiconductor chip mounted on the lower package substrate, and a lower mold layer provided on the lower package substrate to mold the lower semiconductor chip. The lower mold layer may have a trench-shaped first opening through which the lower package substrate is exposed in a substantially line shape. The connection terminals may be electrically connected to the lower package substrate exposed by the first opening and be not in contact with the lower mold layer.