Trench Shield Electrode Isolation Using Conformal HTO Dielectric
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Solution Overview
Problem
The challenge in forming high-quality gate dielectric films and improving the isolation region between gate and shield electrodes in trench-gated MOSFET devices, particularly at small geometries, where complex topographies and trapped charge issues affect device performance.
Innovation Solution
A method involving the formation of a gate dielectric film using an improved LPCVD/HTO process, where a mixture of a semiconductor containing reactant gas and an oxidizing reactant gas is used within a specific temperature and pressure range to deposit a conformal dielectric layer, and a nitride layer is recessed to enhance isolation and reduce trapped charge.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If trench geometries are reduced to increase device cell density, then current carrying capability increases, but gate dielectric film quality deteriorates due to complex topographies
Solution Approach 1:
A planarization layer is formed over the trench structure before depositing the gate dielectric film. This preliminary action creates a flat surface that eliminates the complex topography issues caused by reduced trench geometries, allowing high-quality gate dielectric films to be formed even when device cell density is increased through smaller trench dimensions.
2Reliability
If shield electrode structures with stacked polysilicon are used, then isolation between gate and shield electrodes is improved, but manufacturing complexity increases
Solution Approach 1:
The nitride layer is selectively removed from regions adjacent to the gate electrode, extracting the problematic trapped charge source while preserving the shield electrode structure's isolation function. This selective removal simplifies the overall device structure by eliminating the need for complex stacked polysilicon configurations while maintaining reliable isolation.
Solution Approach 2:
The patent converts the harmful effect of the nitride layer (trapped charge causing threshold voltage shifts) into a beneficial process by selectively removing it in specific regions. The controlled removal transforms a reliability issue into an opportunity to simplify the device structure and improve manufacturing while enhancing device performance.
3Manufacturing precision
If embedded nitride films are used to improve topography, then film quality improves, but trapped charge increases under positive gate bias
Solution Approach 1:
The nitride layer is selectively removed from regions adjacent to the gate electrode while potentially being retained in other areas where it provides topography benefits. This local quality approach allows the device to enjoy the topography advantages of the nitride layer in some regions while eliminating its harmful trapped charge effects in critical regions near the gate electrode.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in improved thickness uniformity and quality of dielectric layers, enhancing the reliability and performance of semiconductor devices by reducing on-resistance and maintaining breakdown voltage.
Implementation Method 1
forming a second dielectric layer overlying the first dielectric layer by reacting a mixture of a semiconductor containing reactant gas and an oxidizing reactant gas within a process chamber in a temperature range from 750 degrees Celsius to 850 degrees Celsius and in a pressure range from 350 milli-torr to 600 milli-torr
Implementation Method 2
forming a gate dielectric film on a semiconductor surface
Data Source
AI summary
In one embodiment, a trench shield electrode layer is separated from a trench gate electrode by an inter-electrode dielectric layer. A conformal deposited dielectric layer is formed as part of a gate dielectric structure and further isolates the trench shield electrode from the trench gate electrode. The conformal deposited dielectric layer is formed using an improved high temperature oxide (HTO) low pressure chemical vapor deposition (LPCVD) process.