Trench SiC MOSFET Doping Layout for Threshold Voltage Control
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Solution Overview
Problem
Designing source and channel implants in trench semiconductor devices is challenging due to the long tails of source implants extending into the underlying channel layer, making it difficult to achieve optimal performance, especially in trench MOSFETs, where the source layer and channel layer lie on top of each other.
Innovation Solution
A method for manufacturing a silicon carbide power semiconductor device with an insulated trench gate electrode involves forming a drift layer, a source layer, and implanting ions of a second conductivity type to create a homogeneous doping region with a doping variation of at most 8% and a thickness of at least 150 nm, arranged between the source and drift layers, using mathematical optimization to control the doping profile.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If source implantation is performed in trench devices, then source layer doping is achieved, but the long tail extends into the channel layer causing doping concentration comparable to or larger than channel doping
Solution Approach 1:
The patent segments the doping process into distinct steps: first forming the source layer with appropriate doping, then performing channel implantation separately. This segmentation allows independent optimization of source and channel doping profiles, preventing the long tail effect from compromising channel doping precision.
Solution Approach 2:
The source layer is formed preliminarily before channel implantation. By establishing the source layer first with controlled doping, the subsequent channel implantation can be precisely targeted without interference from source doping tails, enabling accurate threshold voltage control.
2Length of moving object
If channel length is determined through implantation in trench devices, then channel length control is achieved, but it becomes difficult to obtain appropriate source and channel layers with optimal performance
Solution Approach 1:
The patent applies local quality by creating distinct doping regions with specific characteristics: the source layer has high doping concentration for carrier supply, while the channel layer has precisely controlled lower doping for threshold voltage control. Each region is optimized independently for its specific function, ensuring overall device reliability.
Solution Approach 2:
The patent changes doping parameters (concentration, energy, dose) between source and channel implantation steps. By adjusting these parameters independently for each layer, the invention achieves optimal source and channel characteristics, resolving the difficulty of obtaining both appropriate source and channel layers simultaneously.
3Productivity
If high cell density is implemented, then device integration is improved, but drain-induced barrier lowering and threshold voltage variability increase
Solution Approach 1:
The source layer is formed preliminarily with optimized doping before channel implantation. This preliminary action ensures that even at high cell densities, the source doping does not create excessive tails that would cause DIBL and threshold voltage variability, allowing high integration while maintaining electrical stability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the variability of the effective doping profile, enhances control over the threshold voltage, and minimizes vulnerability to drain-induced barrier lowering, enabling improved performance in trench MOSFETs and IGBTs.
Implementation Method 1
implanting ions of a second conductivity type, which is different than the first conductivity type into the drift layer to produce an implant layer of the second conductivity type with a homogeneous doping region
Data Source
AI summary
A power semiconductor device comprises a drift layer of a first conductivity type, a source layer of the first conductivity type on the drift layer, with an insulated trench gate electrode which extends through the source layer into the drift layer, and an implant layer of a second conductivity type different than the first conductivity type with a homogeneous doping region having a doping variation of at most 8%. The homogeneous doping region is arranged between the source layer and the drift layer and has a homogeneous doping region thickness of at least 150 nm. A method is provided for producing a power semiconductor device with an insulated trench gate electrode.