Trench Silicide Cross-Coupling for Logic Cell Design
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As technology nodes advance beyond 14 nm, lithography resolution becomes insufficient to print connected gates in cross-coupling structures, leading to design congestion and integration complexity in logic cells due to tight spacing among source/drain contacts and trench silicide, which disconnects pMOS and nMOS gates.
Innovation Solution
A trench silicide (TS) layer is formed between gate structures to cross-couple disconnected gates, with the TS layer crossing the gate cut region and connected by contacts on either side, allowing for cross-coupling of pMOS and nMOS gate transistors while relieving design congestion by pushing the cross-coupling to a lower level than middle of line layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If gate contacts and S/D contacts are formed on the same level using middle of line layers, then cross coupling of gates is achieved, but design congestion increases due to tight spacing among contacts and trench silicide
Solution Approach 1:
The patent moves the cross-coupling connection from the middle of line layer level to a lower trench silicide layer level. By forming the trench silicide layer between source/drain regions and using it as the cross-coupling connection layer, the invention changes the vertical dimension of the cross-coupling structure, thereby reducing congestion at the middle of line layer level and improving design flexibility.
2Manufacturing precision
If lithography resolution is used to print connected gates, then cross coupling structure is formed, but spacing constraints prevent proper formation at 14 nm and beyond
Solution Approach 1:
The patent segments the cross-coupling structure into two parts: the trench silicide layer formation (using self-aligned processes) and the gate structure formation. By separating these processes and using self-aligned trench silicide formation, the invention eliminates the need for lithography to print connected gates, thereby enabling scalability to 14 nm and beyond while maintaining manufacturing precision.
3Device complexity
If trench silicide layer is formed between source/drain regions, then cross coupling is enabled at lower level, but additional process steps are required
Solution Approach 1:
The patent merges the trench silicide formation process with the existing source/drain region processing. The trench silicide layer is formed self-aligned between source/drain regions using the same silicide deposition and etch processes already required for source/drain contact formation, thereby minimizing additional process complexity while enabling cross-coupling at the lower level.
Data Source
AI summary
A method of forming a logic cell utilizing a TS gate cross-couple construct and the resulting device are provided. Embodiments include forming active fins and dummy fins on a substrate, the dummy fins adjacent to each other and between the active fins; forming STI regions between and next to the active and dummy fins; forming gate structures in parallel across the active and dummy fins; forming a gate cut region by cutting the gate structures between the dummy fins; forming a TS layer between the gate structures, the TS layer crossing the gate cut region; and forming a contact connecting a gate structure and the TS layer on a first side of the gate cut region and forming a contact connecting a gate structure and the TS layer on a second side of the gate cut region, the TS layer and contacts cross coupling the gate structures.