Trench Silicide Cut for Zero TS Extension
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Solution Overview
Problem
Current semiconductor devices beyond the 14 nm technology node face challenges with large cell height, reduced trench silicide (TS) contact area, and resulting resistance penalties during cell-height scaling.
Innovation Solution
A process involving the formation of high-k metal gates, epitaxial raised source/drain structures, planar self-aligned contact caps, and a two-stage trench silicide cut to minimize TS extension past the active fins, allowing for cell-height scaling without contact area loss or resistance penalty.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If TS extends past the fins to ensure robust contact, then contact reliability is improved, but cell height increases resulting in resistance penalty
Solution Approach 1:
The trench silicide formation is divided into two distinct stages: first forming TS over the RSD regions, then performing a second cut to remove TS that extends beyond the fin regions. This segmentation allows the contact formation process to achieve both robust contact over the RSD and proper alignment with the fins, eliminating the need for TS to extend past the fins while maintaining contact reliability.
Solution Approach 2:
The first TS cut is performed preliminarily to establish TS coverage over the RSD regions before the final device structure is completed. This preliminary action ensures that when the second cut is performed to remove excess TS, the contact area over the RSD is already established, preventing contact area loss while achieving the desired cell height scaling.
2Length of moving object
If cell height is scaled down for advanced nodes, then device density is improved, but contact area is reduced resulting in resistance penalty
Solution Approach 1:
The contact formation is segmented into two distinct cutting operations: the first cut establishes TS coverage over the RSD regions to ensure adequate contact area, while the second cut removes TS extending beyond the fin regions. This segmentation decouples the contact area determination from the cell height scaling, allowing cell height to be reduced for higher density while the first cut ensures sufficient contact area is maintained over the RSD.
Solution Approach 2:
The self-aligned contact (SAC) structure is utilized where the TS formation is automatically aligned with the RSD and fin regions through the sequential cutting process. The first cut creates TS that naturally covers the RSD contact areas, and the second cut removes excess TS without affecting the contact area over the RSD. This self-alignment mechanism ensures that contact area is preserved during cell height scaling without requiring additional alignment steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables effective cell-height scaling for the 14 nm technology node and beyond, maintaining contact area and reducing resistance, thereby improving device performance and yield.
Implementation Method 1
planarizing the metal layer down to the upper surface of the SAC caps
Implementation Method 2
forming first and second oxide and nitride stacks above the first and second pairs of RSD
Implementation Method 3
etching the metal layer proximate to the oxide and nitride stacks to a thickness of 5 nm to 15 nm
Implementation Method 4
forming an ILD over the substrate
Data Source
AI summary
A method of forming a logic or memory cell with less than or equal to 0 nm of TS extending past the active fins and the resulting device are provided. Embodiments include forming gates across pairs of fins on a substrate; forming pairs of RSD between the gates on the fins; forming a planar SAC cap on each of the gates; forming a metal layer over the substrate coplanar with the SACs; forming a TS structure in the metal layer over the fins, the TS structure formed over the pairs of RSD, each upper portion having a width equal to or less than an overall width of a pair of fins; forming spacers on opposite sides of the upper portions; removing the metal layer between adjacent spacers; forming an ILD over the substrate; and forming a CA on each upper portion and a CB on a gate through the ILD.