Trench Silicide Contact Resistance Reduction via Liner Extraction
Solution Overview
Problem
Conventional semiconductor devices face increased middle-of-the-line (MOL) resistance due to high-resistance interfaces between contact area metals and trench silicide regions, primarily caused by the high resistivity of titanium nitride liners used in metallization.
Innovation Solution
A method is developed to manufacture semiconductor devices without a high-resistance interface between contact area metals and trench silicide regions by forming a silicide region, a gate structure, and dielectric layers, then selectively removing portions of the liner layers to expose the silicide region for direct contact with the contact layer, thereby maintaining desirable MOL resistance without delamination.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a titanium nitride liner layer is positioned between the contact area metal layer and the trench silicide region, then metal delamination is prevented, but middle-of-the-line resistance increases due to high resistivity of the liner
Solution Approach 1:
The patent extracts the harmful high-resistivity titanium nitride liner layer from the contact area by selectively removing it through the opening formation process, while preserving the liner layer in other critical areas for delamination prevention
Solution Approach 2:
The patent applies different liner layer configurations to different locations: removing the liner in the contact area where low resistance is needed, while maintaining the liner layer in other areas where delamination prevention is critical
2Manufacturing precision
If the liner layer is completely removed to reduce resistance, then middle-of-the-line resistance decreases, but metal delamination risk increases
Solution Approach 1:
The patent selectively extracts the liner layer only from the contact area through controlled opening formation, leaving the liner layer intact in other areas to maintain delamination prevention while achieving low resistance in the contact region
Solution Approach 2:
The patent creates local quality differentiation by having no liner in the contact area (for low resistance) while maintaining liner coverage in other areas (for delamination prevention)
Data Source
AI summary
A method for manufacturing a semiconductor device comprises forming a silicide region on a semiconductor substrate, forming a gate structure on the semiconductor substrate adjacent the silicide region, forming a dielectric layer on the gate structure and on the silicide region, forming a first liner layer on the dielectric layer, removing a portion of the first liner layer and a portion of the dielectric layer to form an opening exposing a top surface of the silicide region, forming a second liner layer on the first liner layer and on sides and a bottom of the opening, removing a portion of the second liner layer from a top surface of the first liner layer and from the bottom of the opening to re-expose a portion of the top surface of the silicide region, and forming a contact layer in the opening directly on the re-exposed portion of the top surface of the silicide region.