Trench Silicide Contacts via Selective Isotropic Etching
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Solution Overview
Problem
In semiconductor processing, the scaling of devices leads to spacer erosion and increased risk of shorts between source/drain and gate contacts due to thinning of sidewall spacers, resulting in unpredictable epi semiconductor material formation and potential device failure or suboptimal performance.
Innovation Solution
A method involving isotropic etching of a dielectric layer to form self-aligned contacts, using a nitride material as a bottom dielectric layer to maintain spacer thickness and employing a selective etch process that minimizes damage to spacers, ensuring better oxide etch selectivity and control over critical dimensions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the etching process duration is increased to clear spacer material from source/drain surfaces, then the spacer thickness is reduced (particularly at corners), but this leads to exposure of gate electrode material and undesirable epi semiconductor material formation
Solution Approach 1:
The etching process is divided into two distinct stages: a first anisotropic etching step that selectively removes spacer material from source/drain surfaces, and a second isotropic etching step that clears remaining material from horizontal surfaces. This segmentation allows each step to be optimized for its specific function, preventing over-etching and spacer thinning while ensuring complete material removal where needed.
Solution Approach 2:
The patent employs a periodic, multi-step etching sequence with alternating anisotropic and isotropic steps. This periodic action enables controlled, incremental removal of spacer material while periodically reassessing the etching state, thereby maintaining spacer thickness uniformity and preventing exposure of gate electrode material that would lead to defective epi formation.
2Productivity
If sidewall spacer width is decreased to increase packing density, then more active regions can be packed, but the protective capability of the spacer is reduced, leading to epi material formation on gate electrodes
Solution Approach 1:
The patent introduces a thin liner layer as an intermediary between the gate electrode and the sidewall spacer. This liner layer provides an additional protective barrier that enhances gate electrode protection even when the spacer width is reduced for higher packing density. The liner acts as a mediator that prevents direct exposure of the gate electrode to epi semiconductor material formation.
3Manufacturing precision
If anisotropic etching is used to clear spacer material, then directional removal is achieved, but selectivity is insufficient, causing damage to dielectric layers and gate structures
Solution Approach 1:
The patent changes the etching parameters by switching between anisotropic and isotropic etching modes in sequence. The anisotropic step provides directional removal with controlled selectivity, while the subsequent isotropic step compensates for any damage to dielectric layers and gate structures. This parameter change strategy allows achieving both directional material removal and protection of sensitive structures.
Solution Approach 2:
The patent converts the potential harm of anisotropic etching (damage to dielectric layers and gate structures) into a benefit by following it with an isotropic etching step. The isotropic step, while non-directional, selectively removes damaged or excess material without further harming protected structures, thereby transforming the harmful effect of the first step into a controlled process outcome.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach maintains spacer thickness, reduces the risk of shorts, and achieves target design rule specifications by preserving dielectric material and preventing undesirable epi semiconductor material formation on gate electrodes, thereby enhancing the reliability and performance of semiconductor devices.
Implementation Method 1
an isotropic etch process to expose the source and drain regions and form trenches in the nitride material where the source and drain regions are accessible
Implementation Method 2
The isotropic etch is super selective (e.g., etches oxide:nitride at a ratio of 200:1 or greater)
Data Source
AI summary
A method for forming self-aligned contacts includes patterning a mask between fin regions of a semiconductor device, etching a cut region through a first dielectric layer between the fin regions down to a substrate and filling the cut region with a first material, which is selectively etchable relative to the first dielectric layer. The first dielectric layer is isotropically etched to reveal source and drain regions in the fin regions to form trenches in the first material where the source and drain regions are accessible. The isotropic etching is super selective to remove the first dielectric layer relative to the first material and relative to gate structures disposed between the source and drain regions. Metal is deposited in the trenches to form silicide contacts to the source and drain regions.