Nonvolatile Memory Cell Area Reduction via Trench Source Layer
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Solution Overview
Problem
Conventional split gate type nonvolatile semiconductor memory devices face challenges in miniaturization due to the need for a high coupling ratio between the source layer and the floating gate, which increases the memory cell size and hinders further reduction in size.
Innovation Solution
The design incorporates trapezoid-shaped trenches with asymmetric sidewalls and ion-implanted N+ type source layers, reducing the memory cell area while enhancing the coupling ratio between the source layer and the floating gate, and utilizing a thicker gate insulation film to improve data retention and program performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the overlapping area between the source layer and floating gate is increased to achieve high coupling ratio, then the writing performance is improved, but the memory cell area increases
Solution Approach 1:
The source layer is extended from a planar structure to a three-dimensional structure that includes the bottom surface and sidewalls of the trench. This vertical extension into the trench dimension allows the source layer to overlap with the floating gate in multiple spatial dimensions, achieving high coupling ratio without increasing the planar memory cell area.
Solution Approach 2:
The source layer is nested within the trench structure, with portions of the source layer positioned on the bottom surface and sidewalls of the trench. The floating gate is positioned within the trench, creating a nested configuration where the source layer surrounds portions of the floating gate, maximizing the overlapping area within a compact space.
2Area of stationary object
If the memory cell size is reduced for miniaturization, then the integration density is improved, but the coupling ratio between source layer and floating gate decreases
Solution Approach 1:
By utilizing the vertical dimension of the trench, the source layer can achieve extensive overlap with the floating gate without requiring a large planar area. The source layer extends onto the sidewalls and bottom of the trench, creating multiple overlap regions that maintain high coupling ratio in miniaturized cells.
Solution Approach 2:
The source layer is formed as a composite structure with different portions (bottom surface portion and sidewall portion) that work together to achieve high coupling ratio. This composite configuration allows the source layer to effectively couple with the floating gate while occupying minimal planar space.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the memory cell area by approximately 75-80% compared to conventional designs, enhancing writing performance and data retention while maintaining efficient program characteristics.
Implementation Method 1
the electrons of the electron current are accelerated by a high electric field at the PN junction formed between the N+ type source layer 102 and the P type well layer 101, and become high energy hot electrons
Implementation Method 2
Some of the hot electrons are absorbed in the FG 105 that has a high potential by capacitive coupling with the N+ type source layer 102
Implementation Method 3
electrons absorbed in the FG 105 are taken out from the FG 105 and absorbed in the CG 107 through a thin portion of the tunnel insulation film 106 as a Fowler-Nordheim tunnel current
Data Source
AI summary
The invention enhances program performance by increasing a coupling ratio between an N+ type source layer and a floating gate and reduces a memory cell area. Trenches are formed on the both sides of an N+ type source layer. The sidewalls of the trench includes first and second trench sidewalls that are parallel to end surfaces of two element isolation layers, a third trench sidewall that is perpendicular to the STIs, and a fourth trench sidewall that is not parallel to the third trench sidewall. The N+ type source layer is formed so as to extend from the bottom surface of the trench to the fourth trench sidewall, largely overlapping a floating gate, by performing ion-implantation of arsenic ion or the like in a parallel direction to the third trench sidewall and in a perpendicular direction or at an angle to a P type well layer from above the trench having this structure.