Trench Spacer Region Enhances RBSOA in Semiconductor Devices
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Solution Overview
Problem
Conventional trench semiconductor structures lack sufficient reverse biased safe operating area (RBSOA) due to the absence of p+-type regions below n+-type source regions, making them vulnerable to mask misalignment issues.
Innovation Solution
Incorporating shallower first-conductivity-type regions and a second-conductivity-type trench spacer region with higher impurity concentration, positioned closer to the back surface than the first-conductivity-type regions, to enhance RBSOA by creating a trench spacer region that overlaps with the first-conductivity-type regions and is separated from the trench gates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If p+-type regions are omitted to face the back surfaces of n+-type source regions to make gaps between trench gates smaller, then device area is reduced, but reverse biased safe operating area (RBSOA) becomes insufficient
Solution Approach 1:
The invention introduces a trench spacer region that extends in the depth direction (third dimension) beneath the n+-type source regions. This vertical extension allows the spacer region to provide RBSOA protection without occupying additional lateral space, thus resolving the contradiction between reducing device area and maintaining sufficient RBSOA.
Solution Approach 2:
The trench spacer region acts as an intermediary structure between the n+-type source regions and the substrate. It provides the necessary electrical characteristics for RBSOA protection while being spatially separated from the trench gates, enabling area reduction without compromising reliability.
2Ease of manufacture
If p+-type regions are not provided below n+-type source regions, then manufacturing process is simplified, but sufficient RBSOA cannot be assured in case of mask misalignment
Solution Approach 1:
The trench spacer region serves as an intermediary structure that provides RBSOA protection without requiring precise mask alignment like traditional p+-type regions. By being formed as a separate entity beneath the source regions, it simplifies the manufacturing process while ensuring reliability even with mask misalignment.
Solution Approach 2:
The trench spacer region is positioned beforehand beneath the n+-type source regions to provide a safety cushion for RBSOA protection. This pre-positioned protective layer ensures that even if mask alignment is not perfect during subsequent processing steps, sufficient RBSOA is maintained.
3Reliability
If trench spacer region is positioned closer to back surface than first-conductivity-type regions, then RBSOA is enhanced, but device structure becomes more complex
Solution Approach 1:
The trench spacer region utilizes the depth direction (third dimension) to provide RBSOA protection by extending beneath the n+-type source regions. This vertical arrangement enhances RBSOA without adding lateral complexity, as the spacer region aligns with existing device features in the planar direction.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively improves RBSOA by ensuring the semiconductor device maintains a large safe operating area, reducing the risk of damage from reverse bias and maintaining stable performance even with advancements in microfabrication.
Implementation Method 1
a second-conductivity-type trench spacer region spaced away from the one or more trench gates, where the trench spacer region has a higher concentration than the second-conductivity-type regions
Data Source
AI summary
A semiconductor device includes one or more trench gates extending in a first direction in plan view, one or more first-conductivity-type regions spaced away from each other in the first direction, where the first-conductivity-type regions are shallower than the trench gates, one or more second-conductivity-type regions alternating with the first-conductivity-type regions in the first direction, where the second-conductivity-type regions are shallower than the trench gates and deeper than the first-conductivity-type regions, and a second-conductivity-type trench spacer region spaced away from the one or more trench gates, where the trench spacer region has a higher concentration than the second-conductivity-type regions. Here, the trench spacer region is positioned within the first-conductivity-type regions in plan view and closer to a back surface of the semiconductor device than the first-conductivity-type regions are.