Trench Switching Element Layout for Current Surge Suppression
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Solution Overview
Problem
Conventional trench-gate type switching elements experience current concentration and recovery surge issues due to the low density of connection regions, leading to potential reliability concerns during operation.
Innovation Solution
The switching element incorporates a semiconductor substrate with inter-trench semiconductor layers, deep regions, and connection regions arranged in a specific pattern to distribute current flow, reducing current concentration and avalanche current stress by ensuring a Manhattan distance of 1 between non-connection and connection intersection portions, thereby restricting recovery and avalanche currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If connection regions are sparsely distributed in conventional trench-gate type switching elements, then device complexity is reduced, but current concentration and recovery surge occur leading to reliability deterioration
Solution Approach 1:
The connection regions are segmented into a regular grid pattern with specific spacing (3-4 intervals between connection regions). This segmentation distributes the current flow paths uniformly across the semiconductor substrate, preventing current concentration at specific locations while maintaining a manageable density that does not excessively complicate the device structure.
Solution Approach 2:
The patent specifies precise parameter ranges for the connection region distribution pattern, including the number of intervals (3-4) between connection regions and the Manhattan distance (1) from non-connection intersection portions to closest connection regions. These parameter changes optimize the balance between current distribution effectiveness and device complexity.
2Reliability
If connection regions are densely distributed to reduce current concentration, then reliability improves, but manufacturing complexity and cost increase
Solution Approach 1:
The patent defines specific parameter ranges (3-4 intervals between connection regions, Manhattan distance of 1) that optimize the balance between current distribution effectiveness and manufacturability. These parameters ensure sufficient current distribution without creating an excessively dense pattern that would complicate manufacturing processes.
Solution Approach 2:
The connection regions are arranged to provide uniform local quality across the semiconductor substrate. Each region follows the same spacing pattern, ensuring consistent current distribution characteristics throughout the device while maintaining manufacturing simplicity through repetition of a standardized pattern.
3Reliability
If connection regions are arranged in irregular patterns to optimize current flow, then current distribution improves, but manufacturing precision requirements increase
Solution Approach 1:
The connection regions are segmented into a regular grid pattern with defined spacing intervals (3-4 between regions). This regular segmentation provides predictable current distribution characteristics while being straightforward to manufacture using standard photolithography and deposition processes, avoiding the need for complex irregular patterns.
4Reliability
If the number of connection regions is increased to reduce on-resistance, then electrical performance improves, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent specifies optimal parameter ranges for connection region density (3-4 intervals between regions) that achieve sufficient current distribution to maintain low on-resistance while avoiding excessive density that would unnecessarily increase device complexity and manufacturing cost.
Data Source
AI summary
A switching element includes a semiconductor substrate having inter-trench semiconductor layers each interposed between trenches and including a body region. The semiconductor substrate further includes deep regions and connection regions that connect the deep regions and the body region. The connection regions are arranged in rows. Intersection portions of the inter-trench semiconductor layers and the rows include connection intersection portions at which the connection regions are disposed and non-connection intersection portions at which the connection regions are not disposed. The connection intersection portions and the non-connection intersection portions are repeatedly arranged according to a reference pattern in which a number of the non-connection intersection portions interposed between adjacent two of the connection intersection portions is three or four, and a Manhattan distance of each of the non-connection intersection portions to closest one of the connection intersection portions is 1.