Dual-Gate Trench TFT Layout for Low-Capacitance Channel Control
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Solution Overview
Problem
There is a need for improved thin film transistors (TFTs) that provide enhanced performance and density, particularly in applications such as embedded dynamic random access memory (eDRAM), where existing TFTs face challenges in short channel control, contact resistance, and parasitic gate to source/drain capacitance.
Innovation Solution
The development of dual gate trench shaped thin film transistors with a non-planar semiconductor layer, featuring a first gate electrode structure adjacent to a first gate dielectric layer and a second gate electrode structure within a trench adjacent to the semiconductor layer, providing dual gate control and improved performance through reduced capacitance and increased effective gate lengths without increasing the lateral footprint.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional planar TFT structures are used, then manufacturing is simple, but short channel control is poor
Solution Approach 1:
The patent transitions from a planar two-dimensional gate structure to a three-dimensional trench-shaped gate structure that extends vertically into the semiconductor layer. This dimensional change allows the gate to control the channel from multiple spatial positions (top and sidewalls), significantly improving short channel control while managing the complexity through systematic fabrication processes.
2Reliability
If gate electrode structures are extended to improve control, then short channel control improves, but parasitic gate to source/drain capacitance increases
Solution Approach 1:
The gate dielectric layer is engineered with varying thicknesses at different locations: thinner at the top surface for strong vertical control, and thicker at the sidewalls to reduce parasitic capacitance between the gate and source/drain regions. This local differentiation of dielectric quality allows simultaneous optimization of control and capacitance reduction.
Solution Approach 2:
The trench-shaped gate structure distributes the gate control function across multiple spatial dimensions (vertical and lateral), allowing the effective gate length to increase without proportionally increasing the lateral footprint that would generate parasitic capacitance. The three-dimensional configuration separates control function from capacitance generation.
3Productivity
If device density is increased, then productivity improves, but contact resistance increases
Solution Approach 1:
The trench-shaped gate structure increases the effective gate length in the vertical dimension without expanding the lateral footprint, allowing higher device density while maintaining adequate source and drain contact areas. This dimensional separation enables density improvement without compromising contact quality.
Data Source
AI summary
Disclosed herein are dual gate trench shaped thin film transistors and related methods and devices. Exemplary thin film transistor structures include a non-planar semiconductor material layer having a first portion extending laterally over a first gate dielectric layer, which is over a first gate electrode structure, and a second portion extending along a trench over the first gate dielectric layer, a second gate electrode structure at least partially within the trench, and a second gate dielectric layer between the second gate electrode structure and the first portion.