Trench Transistor Buffer Layer Design for Short-Channel Effect
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Solution Overview
Problem
As display devices evolve with higher resolution and reduced dead space, the area allocated to transistors decreases, leading to deteriorated electrical characteristics due to the short-channel effect.
Innovation Solution
The implementation of a display device design that includes a relatively long channel region in a limited area by using a trench or fin structure, along with a specific barrier and buffer layer configuration, to improve transistor device characteristics and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the transistor area is reduced to accommodate higher resolution display, then the display resolution is improved, but the electrical characteristics of the transistor deteriorate due to short-channel effect
Solution Approach 1:
The patent transitions from a planar channel structure to a three-dimensional trench or fin channel structure. By forming the channel region within a trench or fin that extends vertically into the substrate, the effective channel length is increased in the vertical dimension while maintaining a compact footprint in the planar dimension. This allows the transistor to achieve longer channel length (improving electrical characteristics) without increasing the overall device area (preserving display resolution).
Solution Approach 2:
The channel region is nested within the trench or fin structure that is itself embedded in the substrate. The trench or fin acts as a container that houses the channel forming layer, creating a hierarchical structure where the channel region is nested within the trench/fin, which is nested within the substrate. This nesting approach maximizes the use of vertical space to achieve longer effective channel length without proportionally increasing the planar device area.
2Reliability
If a trench or fin structure is used to increase channel length, then transistor reliability is improved, but step coverage issues arise during manufacturing
Solution Approach 1:
The buffer layer is segmented into multiple thin sub-layers (first buffer layer, second buffer layer, third buffer layer) stacked vertically. Each sub-layer has a thickness of 50-200 nm and is formed sequentially. This segmentation allows better control of step coverage during deposition processes, as each thin layer can be deposited with improved uniformity compared to a single thick layer, while still providing sufficient total buffer thickness (500-800 nm) to mitigate step coverage issues.
Solution Approach 2:
The buffer layer composition is varied locally across different sub-layers. The first buffer layer contains a first material, the second buffer layer contains a second material, and the third buffer layer contains a third material. This local quality differentiation allows optimization of step coverage and electrical characteristics in each specific region of the buffer stack, addressing the step coverage issue while maintaining transistor performance.
Data Source
AI summary
A display device according to an embodiment includes a barrier layer on a substrate and including a trench, a first buffer layer on the barrier layer and arranged along a profile of the trench, a second buffer layer on the first buffer layer and arranged along a profile of the first buffer layer, a semiconductor layer on the second buffer layer and including a channel region overlapping the trench, a gate insulating layer on the semiconductor layer and overlapping the channel region, and a gate electrode on the gate insulating layer and overlapping the channel region, and a thickness of the first buffer layer is thinner than a thickness of the second buffer layer.