Field Effect Trench Transistor ESD Protection via Inactive Trench Integration
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Solution Overview
Problem
Field effect trench transistors face challenges in protecting the gate oxide from electrostatic discharge (ESD) pulses, particularly due to exposed leads that can lead to component destruction, and existing solutions like planar diodes in IGBTs require significant space and are not easily integrable into field effect trench transistors.
Innovation Solution
Integrating polysilicon diodes or zener diodes in inactive trenches of field effect trench transistors, where no gate electrodes are present, allows for ESD protection with minimal space requirements and compatibility with existing process flows, with diodes connected in series or between gate and drain for enhanced protection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If planar diodes are provided between source metallization and gate metallization to protect the gate oxide from ESD pulses, then the gate oxide is protected from ESD damage, but the space requirement becomes very large and integrability into the process flow deteriorates
Solution Approach 1:
The patent merges the ESD protective diode function with the existing inactive trenches in the FoM-optimized field effect trench transistor. Instead of adding separate planar diodes that would require large space, the protective diodes are integrated into the already-present inactive trenches, combining two functions (ESD protection and FoM optimization) into a single structural element.
Solution Approach 2:
The inactive trenches, originally designed solely for FoM optimization to reduce gate charge, are given a dual function by integrating ESD protective diodes within them. This multi-functional approach allows the same structural feature to provide both capacitance reduction and electrostatic discharge protection, eliminating the need for separate dedicated ESD protection structures.
2Reliability
If planar diodes are provided between source metallization and gate metallization to protect the gate oxide from ESD pulses, then the gate oxide is protected from ESD damage, but the integration into process flow becomes difficult
Solution Approach 1:
The patent merges the ESD protective diode function with the existing inactive trenches in the FoM-optimized field effect trench transistor. Instead of adding separate planar diodes that would require large space, the protective diodes are integrated into the already-present inactive trenches, combining two functions (ESD protection and FoM optimization) into a single structural element.
Solution Approach 2:
The inactive trenches are created in advance as part of the standard FoM optimization process flow. The ESD protective diodes are then formed within these pre-existing trenches during subsequent processing steps, allowing the ESD protection structure to be built upon an already-established foundation rather than requiring a complete redesign of the manufacturing sequence.
3Adaptability or versatility
If exposed leads are used for connecting driver chip and field effect power transistor, then flexibility in lead configuration is achieved, but the signal exchange becomes subject to fluctuations and components are exposed to ESD pulse damage
Solution Approach 1:
The patent applies preliminary anti-action by providing ESD protective diodes that preemptively counteract potential ESD damage before it can reach the gate oxide. The protective diodes are positioned and biased to clamp or divert ESD pulses away from sensitive components, creating a pre-established defense mechanism that activates when ESD threats occur.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively protects the gate oxide from ESD while optimizing space usage and integrating seamlessly with existing fabrication processes, achieving robust ESD protection and reduced leakage currents.
Implementation Method 1
a series of polysilicon protective diodes and/or zener diodes is integrated in one or more of the inactive trenches
Implementation Method 2
polysilicon zener diodes that serve for the zenering of the trench transistor
Data Source
AI summary
One embodiment of the invention relates to a field effect trench transistor with a multiplicity of transistor cells that are arranged like an array and whose gate electrodes are arranged in active trenches formed in a semiconductor body. Inactive trenches are arranged in the array of the transistor cells, there being no gate electrodes situated in said inactive trenches, and a series of polysilicon diodes are integrated in one or more of the inactive trenches which diodes, for protection against damage to the gate oxide through ESD pulses, are contact-connected to a source metallization at one of their ends and to a gate metallization at their other end, and/or alternatively or additionally one or more polysilicon zener diodes connected in series is or are integrated in the inactive trench or trenches and contact-connected to the gate metallization by one of its or their ends and to drain potential by its or their other end.