Trench Transistor Field Electrode Layout for Gate Dielectric Protection
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Solution Overview
Problem
Conventional SiC based transistor devices face challenges with high electric fields damaging the gate dielectric and limited cell pitch due to the implantation process for forming JFET regions, which increases costs and reduces the minimal possible cell pitch.
Innovation Solution
The transistor device incorporates a field electrode dielectrically insulated from the drift region by a high-k dielectric, extending deeper into the semiconductor body than the gate trench, and connected to the source node, which helps in protecting the gate dielectric from high electric fields and allows for a more compact cell design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If doped regions (JFET regions) are formed using an implantation process to protect the gate dielectric from high electric fields, then the gate dielectric is protected, but the manufacturing cost increases and the cell pitch cannot be reduced further
Solution Approach 1:
The invention extracts the JFET region formation step from the manufacturing process by replacing the implantation process with a selective growth process. The field electrode structure is formed directly during the semiconductor body growth process, eliminating the need for separate implantation steps and thick mask formation, thereby reducing manufacturing cost while maintaining gate dielectric protection.
Solution Approach 2:
The field electrode structure is formed preliminarily during the semiconductor body growth process before subsequent processing steps. This preliminary formation of the field electrode with complementary doping type creates the protective structure in advance, eliminating the need for later implantation steps and enabling further cell pitch reduction.
2Reliability
If doped regions (JFET regions) are formed using an implantation process to protect the gate dielectric, then the gate dielectric is protected, but the cell pitch cannot be reduced due to lateral straggling of implanted dopant atoms
Solution Approach 1:
The invention replaces the mechanical implantation process with a chemical growth process. The field electrode structure is formed through selective epitaxial growth on exposed semiconductor surfaces, which provides precise lateral definition without the lateral straggling inherent in ion implantation. This substitution enables significantly reduced cell pitch while maintaining effective field protection.
3Reliability
If pn-junctions are formed between the drift region and the JFET regions to protect the gate dielectric, then the gate dielectric is protected in blocking state, but space-charge regions reduce the width of the electrically conducting path in on-state
Solution Approach 1:
The invention applies local quality by forming the field electrode structure with complementary doping type in specific locations adjacent to the gate trench. This creates localized field protection zones that prevent high electric fields from reaching the gate dielectric, while the selective positioning minimizes the impact on the overall conducting path width in the on-state, thereby reducing conduction losses compared to conventional JFET regions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the voltage blocking capability and reduces on-resistance while protecting the gate dielectric, enabling a more efficient and cost-effective transistor device with improved cell pitch and reduced conduction losses.
Implementation Method 1
The field electrode is dielectrically insulated from the drift region by a high-k dielectric
Data Source
AI summary
A transistor device and a method for manufacturing a transistor device are disclosed. The transistor device includes a semiconductor body and a plurality of transistor cells. Each transistor cell includes: a drift region, a body region, and a source region; a gate electrode connected to a gate node; and a field electrode connected to a source node. The gate electrode is dielectrically insulated from the body region by a gate dielectric, and is arranged in a first trench extending from a first surface into the semiconductor body. The field electrode is dielectrically insulated from the drift region by a high-k dielectric, and is arranged in a second trench. The second trench extends from the first surface into the semiconductor body and is spaced apart from the first trench, and the field electrode extends at least as deep as the first trench into the semiconductor body.