Trench Transistor Gate Field Plate RESURF Effect
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Solution Overview
Problem
Conventional high voltage field-effect transistors achieve high breakdown voltage at the expense of switching speed due to increased gate-to-drain capacitance from larger drain regions, compromising reliability and performance.
Innovation Solution
The introduction of a gate field plate with a vertical reduced surface (RESURF) effect in the drift region of trench transistors, which reduces surface area and gate-to-drain capacitance, allowing for high breakdown voltage and low on-state resistance without sacrificing switching speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the drain region is expanded to increase breakdown voltage, then breakdown voltage is improved, but gate-to-drain capacitance increases resulting in larger on-state resistance and reduced switching speed
Solution Approach 1:
The patent transitions from a conventional planar drain region to a three-dimensional vertically-oriented drift region extending into the substrate. This dimensional change allows the drift region to provide high breakdown voltage through increased vertical length while maintaining a compact lateral footprint, thereby reducing gate-to-drain capacitance and preserving fast switching speed without the traditional trade-off.
Solution Approach 2:
The drain region is segmented into a vertically-oriented drift region that extends separately into the substrate, distinct from the lateral device structure. This segmentation allows the drift region to be optimized independently for breakdown voltage through vertical extension, while the lateral device dimensions remain compact to minimize capacitance, resolving the contradiction between high voltage and fast switching.
2Reliability
If the drain-to-gate surface area is increased to achieve high breakdown voltage, then breakdown voltage is improved, but on-state resistance increases which negatively impacts switching speed
Solution Approach 1:
The invention moves the breakdown voltage enhancement from the lateral dimension (increased surface area) to the vertical dimension (increased depth into substrate). The vertically-oriented drift region provides the necessary breakdown voltage through its extended length into the substrate while maintaining a small lateral footprint, thus keeping gate-to-drain capacitance low and preserving high switching speed.
Solution Approach 2:
The patent changes the geometric parameters of the drain region by orienting it vertically into the substrate rather than laterally on the surface. This parameter change allows breakdown voltage to be increased through vertical length while maintaining compact lateral dimensions, thereby reducing the drain-to-gate surface area and associated capacitance effects that would slow switching.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables high breakdown voltage and low on-state resistance, enhancing the performance and reliability of transistors by maintaining fast switching speed and reducing gate-to-drain capacitance, while being compatible with current CMOS processes.
Implementation Method 1
The gate field plate introduces vertical reduced surface (RESURF) effect in a drift region of the device
Data Source
AI summary
A method of forming a device is disclosed. A substrate defined with a device region is provided. A gate having an upper and a lower portion is formed in a trench in the substrate in the device region. The upper portion forms a gate electrode and the lower portion forms a gate field plate. First and second surface doped regions are formed adjacent to the gate. The gate field plate introduces vertical reduced surface (RESURF) effect in a drift region of the device.