Trench Vertical Channel Memory Structure for Fine Pattern Limits
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Solution Overview
Problem
The challenge is to enhance the degree of integration and electrical characteristics of semiconductor memory devices while overcoming the limitations of two-dimensional designs, which require expensive equipment for fine pattern formation.
Innovation Solution
A semiconductor memory device is designed with a vertical channel transistor (VCT) configuration, featuring a bit line, protruded insulating patterns, channel patterns made of a first metal oxide, channel interfacial layers, word lines, and capacitors. This configuration allows for improved integration and electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a two-dimensional or planar semiconductor memory device is used, then the manufacturing process is simpler, but the degree of integration is limited and requires expensive equipment for fine pattern formation
Solution Approach 1:
The patent transitions from a two-dimensional planar structure to a three-dimensional vertical structure by forming channel patterns that extend vertically from the substrate surface. The channel patterns are formed along the sidewalls of a trench structure, creating a vertical channel that increases the effective channel area without increasing the planar footprint, thereby achieving higher degree of integration without requiring expensive fine pattern equipment
2Productivity
If the degree of integration is increased to fulfil performance and cost requirements, then product competitiveness improves, but the unit memory cell area must be reduced which requires advanced fine pattern technology
Solution Approach 1:
The invention utilizes vertical dimension by forming channel patterns along the sidewalls of a trench, transforming the memory cell structure from planar to vertical. This increases the effective channel width without reducing the planar area of the unit memory cell, enabling higher degree of integration while avoiding the need for advanced fine pattern equipment
Solution Approach 2:
The channel patterns are formed within the trench structure, nesting the channel formation process within the existing trench geometry. This nested approach allows the channel patterns to be formed using the trench sidewalls as templates, simplifying the patterning process while achieving high degree of integration
Data Source
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AI summary
A semiconductor memory device is provided that includes a bit line on a substrate, a protruded insulating pattern on the bit line, and in a channel trench, first and second channel patterns that extend along sidewalls of the channel trench, and spaced apart from the first channel pattern in the first direction, a channel interfacial layer that extends along the sidewalls of the channel trench, and is in contact with the first channel pattern and the second channel pattern, a first word line between the first channel pattern and the second channel pattern, a second word line between the first channel pattern and the second channel pattern, and is spaced apart from the first word line in the first direction and a first capacitor and a second capacitor, which are electrically connected to the first channel pattern and the second channel pattern.