Trench Via Package Routing for Low-Loss High-Speed Interconnects
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Solution Overview
Problem
Current packaging architectures for high-speed interconnects in IC packages face challenges in scaling bandwidth and reducing signal loss due to limitations in copper interconnect technology, particularly at high data transmission rates above 10 GHz, where dielectric and conductor losses dominate, leading to increased insertion loss and reduced routing density.
Innovation Solution
The implementation of a microelectronic assembly with a package substrate featuring conductive traces and trench vias in dielectric layers, where the trench vias are aligned with underlying traces to increase routing density and reduce loss, utilizing a skip layer architecture with asymmetric implementations to achieve lower insertion loss and higher routing density without sacrificing performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If copper interconnect technology is used for high-speed data transmission above 10 GHz, then signal transmission is enabled, but dielectric and conductor losses dominate causing increased insertion loss
Solution Approach 1:
The patent introduces trench vias that extend vertically through dielectric layers, transitioning from planar routing to three-dimensional routing. This vertical dimension allows signals to bypass lossy horizontal paths and connect IC dies more directly, reducing the effective transmission path length through high-loss dielectric materials and thereby reducing insertion loss at high frequencies above 10 GHz
Solution Approach 2:
The patent segments the interconnect path into multiple components: horizontal traces in metallization layers, vertical trench vias through dielectric layers, and grounded shielding structures. This segmentation allows optimization of each segment's function, with trench vias providing low-loss vertical transmission and grounded structures providing shielding, collectively reducing overall insertion loss
2Productivity
If routing density is increased to scale bandwidth, then more interconnects can be packed, but signal loss increases due to closer spacing
Solution Approach 1:
By utilizing the vertical dimension with trench vias, the patent enables additional routing capacity without increasing lateral density. Multiple trench vias can be stacked vertically through different dielectric layers, allowing bandwidth scaling through vertical layering rather than horizontal crowding, thus maintaining adequate spacing between lateral traces while increasing overall routing capacity
Solution Approach 2:
The patent employs asymmetric routing configurations where trench vias are selectively positioned and sized based on local routing requirements. The trench via structure itself is asymmetric, extending vertically through dielectric layers while maintaining controlled lateral dimensions, allowing optimized spacing and reduced coupling between adjacent interconnects even at high routing densities
3Ease of manufacture
If traditional via routing is used, then manufacturing is simpler, but routing density is limited and loss reduction is insufficient
Solution Approach 1:
The manufacturing process is segmented into distinct stages: forming metallization layers with horizontal traces, creating dielectric layers, and then forming trench vias through the dielectric layers to connect between metallization layers. This segmentation allows each layer type to be optimized independently while maintaining overall manufacturing feasibility through established semiconductor fabrication techniques
Solution Approach 2:
The patent extends traditional planar via routing into the vertical dimension by creating trench vias that traverse multiple dielectric layers. This dimensional extension increases routing density and design flexibility while remaining compatible with existing multi-layer PCB and semiconductor packaging manufacturing processes, requiring only additional patterning and etching steps
Data Source
AI summary
Embodiments of a microelectronic assembly comprise: a package substrate comprising a conductive trace in a dielectric material, the conductive trace surrounded by a conductive structure coupled to a ground connection, the package substrate further comprising metallization layers alternating with dielectric layers of the dielectric material; and an integrated circuit (IC) die coupled to a surface of the package substrate, the IC die being coupled to the conductive trace by a conductive pathway. The dielectric layers and the metallization layers are parallel to the surface of the package substrate, the conductive trace comprises a trench via in one of the dielectric layers, and the conductive structure comprises grounded plates extending across a length and width of the package substrate in metallization layers on either side of the dielectric layer.