Trenched Gate Isolation Structure for Semiconductor Devices
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Solution Overview
Problem
Conventional LOCOS method for forming isolation regions in semiconductor devices results in the 'birds' beak' effect, increasing silicon consumption and limiting process flexibility due to high-temperature requirements, which are detrimental to device miniaturization and packing density.
Innovation Solution
A method involving the formation of trenched gates followed by deposition of insulating layers, where etching processes define the isolation structure, avoiding high-temperature processes and the 'birds' beak' effect, allowing for flexible timing of isolation structure formation and reduced silicon consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If LOCOS method is used to form isolation regions, then electrical isolation between devices is achieved, but birds' beak effect increases silicon consumption
Solution Approach 1:
The patent extracts the isolation function from the substrate surface by forming trenches and filling them with insulating material. This separates the isolation structure from the active silicon area, preventing lateral oxidation and birds' beak effect while maintaining electrical isolation between devices.
Solution Approach 2:
The patent transitions from planar isolation (LOCOS) to three-dimensional trench isolation. By etching vertical trenches and filling them with insulating material, the isolation structure extends into the depth dimension, achieving effective electrical isolation without lateral encroachment on active regions.
2Reliability
If LOCOS method is used to form isolation regions, then electrical isolation is provided, but process flexibility is reduced due to high-temperature requirements
Solution Approach 1:
The patent changes the temperature parameter of the isolation formation process. Instead of requiring high-temperature oxidation (LOCOS), the method uses low-temperature trench etching and insulating material deposition, enabling isolation formation at any stage of the manufacturing process without affecting previously formed devices.
Solution Approach 2:
The patent performs trench formation and insulating material deposition as preliminary actions before final device fabrication. This allows the isolation structure to be established early without requiring subsequent high-temperature processes, providing flexibility for later manufacturing steps.
3Reliability
If LOCOS method is used to form isolation regions, then electrical isolation between active regions is achieved, but active region area is reduced
Solution Approach 1:
The patent extracts the isolation function into separate trench structures filled with insulating material. This removes the isolation requirement from the active silicon surface, preventing lateral oxidation encroachment and maximizing the area available for active device regions while maintaining effective electrical isolation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively provides electrical isolation without the 'birds' beak' effect and reduces silicon consumption, enhancing process flexibility and device miniaturization capabilities.
Implementation Method 1
a first etching process is performed to remove portions of the second insulating layer to expose portions of the first insulating layer. Then, a second etching process is performed to remove the exposed first insulating layer to expose the trenched gates and to define at least an active region.
Data Source
AI summary
A method for manufacturing an isolation structure integrated with semiconductor device includes following steps. A substrate is provided. A plurality of trenched gates is formed in the substrate. A first insulating layer and a second insulating layer are sequentially deposited on the substrate. A first etching process is performed to remove portions of the second insulating layer to expose portions of the first insulating layer. A second etching process is then performed to remove the exposed second insulating layer to expose the trenched gates and to define at least an active region.