Trenched Self-Aligned Guard Ring for Semiconductor Breakdown Voltage
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Solution Overview
Problem
Existing semiconductor devices face premature voltage breakdown due to electric field crowding at device edges, which is exacerbated by surface charges at the dielectric-semiconductor interface, reducing the effectiveness of multiple floating guard ring structures.
Innovation Solution
A method for fabricating a trenched, self-aligned guard ring structure that simultaneously forms trenches for gates and guard rings using a single etching step, ensuring precise alignment and eliminating the impact of surface charges by isolating the guard rings from dielectric surface charges, thereby enhancing breakdown voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple floating guard ring structures are used to reduce electric field crowding and improve breakdown voltage, then breakdown voltage is improved, but the structure becomes very sensitive to surface charges at the dielectric-semiconductor interface which reduces effectiveness and causes breakdown walk-out
Solution Approach 1:
The patent extracts the guard ring structure from the planar configuration and places it into a trench, removing it from direct contact with the dielectric-semiconductor interface where surface charges accumulate. This extraction eliminates the harmful interaction between the guard ring and surface charges while preserving the electric field distribution benefits.
Solution Approach 2:
The patent transitions the guard ring structure from a two-dimensional planar layout to a three-dimensional trenched configuration. By etching trenches into the semiconductor substrate and placing guard rings within these trenches, the structure moves to a different spatial dimension that avoids the charged interface while maintaining electrical functionality.
2Manufacturing precision
If traditional separate fabrication steps are used for forming gates and guard rings, then manufacturing flexibility is maintained, but manufacturing precision and alignment accuracy deteriorate leading to spacing variations
Solution Approach 1:
The patent merges the formation of gates and guard rings into a single etching step. By using a unified mask pattern that defines both gate trenches and guard ring trenches simultaneously, the process achieves precise relative alignment between gates and guard rings without requiring multiple alignment steps, thereby improving manufacturing precision.
Solution Approach 2:
The patent performs preliminary patterning of the mask layer to define both gate and guard ring positions before the etching process. This preliminary action ensures that the relative positions are predetermined and maintained throughout the fabrication process, achieving high alignment accuracy without complex real-time control.
3Reliability
If guard rings are formed at the same depth as gates, then fabrication simplicity is maintained, but electric field distribution is suboptimal reducing breakdown voltage performance
Solution Approach 1:
The patent applies local quality by creating different depths for different structures within the same device. Guard rings are positioned at a greater depth than gates, allowing each structure to be optimized for its specific function: gates at shallower depth for channel control and guard rings at deeper depth for optimal electric field distribution and breakdown voltage enhancement.
Data Source
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AI summary
A guard ring structure for use in a semiconductor device. The guard ring structure includes a semiconductor layer stack having a first layer and a second layer on top of the first layer, gates structures formed in the first layer; and guard rings formed in the first layer. The second layer has a dopant concentration that is higher than the dopant concentration of the first layer. The gates and the guard rings are formed simultaneously using a single mask.