Trenched Power MOSFET Gate Impedance Reduction
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Solution Overview
Problem
Conventional trenched power MOSFET fabrication methods face challenges in reducing gate impedance due to high resistivity of polysilicon gates, which affects switching speed and increases switching loss, and the formation of self-alignment silicide is hindered by the thicker silicon oxide layer on polysilicon gates compared to the epitaxial layer.
Innovation Solution
The method involves forming gate trenches, gate oxide layers, and polysilicon gates, followed by ion implantation and drive-in processes in an oxygen-free environment to prevent silicon oxide formation on polysilicon gates, allowing for the use of the gate oxide layer as a mask for self-alignment silicide formation, thereby reducing gate resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the width and depth of gate trench are reduced for higher integration, then the transistor size is reduced, but the polysilicon gate resistance increases
Solution Approach 1:
The patent changes the chemical composition parameter of the gate material by forming silicide compounds (such as cobalt silicide) on the polysilicon gate surface. This transformation from pure polysilicon to silicide compound dramatically reduces the resistivity, solving the high resistance problem caused by reduced gate dimensions while maintaining the compact transistor structure.
2Reliability
If self-alignment silicide is formed on polysilicon gate, then the gate resistance is reduced, but the process complexity increases due to removal of thick silicon oxide layer
Solution Approach 1:
The patent performs the ion implantation and thermal processing steps in a nitrogen atmosphere instead of oxygen environment. This prevents the formation of thick silicon oxide layers on the polysilicon gate surface, eliminating the need for complex oxide removal steps while enabling direct self-alignment silicide formation, thus reducing process complexity.
Solution Approach 2:
The patent performs ion implantation of silicide-forming elements (such as cobalt) into the polysilicon gate before the final thermal processing step. This preliminary introduction of silicide-forming elements, combined with the nitrogen atmosphere, ensures that silicide forms automatically during the subsequent thermal step without requiring additional processing steps to remove thick oxides.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces the resistance of polysilicon gates, improving switching speed and reducing switching loss by enabling the formation of self-alignment silicide without the complications of thick silicon oxide layers, thus enhancing the efficiency of power converters.
Implementation Method 1
the gate oxide layer as a mask for self-alignment silicide formation
Implementation Method 2
a blanket ion implantation process is performed to implant P-type dopants into the N-type epitaxial layer
Implementation Method 3
the implanted P-type dopants are driven in by undertaking a thermal process, in order to form a P-body
Implementation Method 4
the implanted ion from spreading outwards. But, the polysilicon gates are also exposed. Hence, a silicon oxide layer is formed on the surface of the polysilicon gates
Data Source
AI summary
A fabrication method of a trenched power MOSFET with low gate impedance is provided. The fabrication method comprising the steps of: forming a plurality of trenches in an epitaxial layer; forming a gate oxide layer on the epitaxial layer; forming a plurality of polysilicon gates in the trenches; implanting dopants with a first conductivity type into the epitaxial layer; driving-in the dopants in an oxygen-free environment to form a body; implanting dopants with a second conductivity type into the body; driving-in the dopants with the second conductivity type in an oxygen-free environment to form a plurality of source regions; forming self alignment silicide on the polysilicon gates by using the gate oxide layer as a mask; depositing a dielectric layer on the epitaxial layer and forming a window therein exposing the source regions; and forming a heavily doped region of the first conductivity type in the body beneath the window.