Trenched Transistor Gate Structure for Leakage Control
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Solution Overview
Problem
The challenge in integrated circuit fabrication is to reduce transistor size while maintaining high on-state current (Ion) and minimizing off-state current (Ioff), which is complicated by short channel effects and leakage mechanisms like drain-induced barrier lowering (DIBL), especially in smaller transistors.
Innovation Solution
The proposed solution involves a trenched transistor configuration with a recess having a wide lower region and a narrow upper region, lined with gate dielectric and gate materials, and featuring saddle regions and stepped source/drain regions, which allows for improved Ion while maintaining low Ioff, and enables wider contact surfaces.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If transistor size is reduced to increase integration levels, then device density improves, but short channel effects and leakage current increase
Solution Approach 1:
The patent introduces a three-dimensional FinFET structure with a vertical fin extending from the substrate, transforming the conventional planar two-dimensional channel into a vertical three-dimensional structure. This dimensional change increases the effective channel area and control gate coverage without increasing the lateral footprint, thereby improving device density while maintaining reliable off-state current control through enhanced electrostatic control of the vertical channel.
Solution Approach 2:
The gate structure is nested around the vertical fin channel in a wraparound configuration, with the gate enclosing the fin on multiple sides. This nested arrangement maximizes the gate's control over the channel current while minimizing the device footprint, allowing higher density integration without sacrificing leakage control.
2Quantity of substance
If transistor channel length is reduced to increase integration, then device density improves, but drain-induced barrier lowering (DIBL) increases causing higher off-state current
Solution Approach 1:
The patent transitions from a planar channel to a vertical FinFET channel structure, where the channel extends vertically rather than horizontally. This dimensional change allows for shorter effective channel lengths in the lateral direction (increasing density) while the vertical fin structure provides enhanced gate control that suppresses DIBL effects, maintaining low off-state current despite reduced channel dimensions.
Solution Approach 2:
The patent employs selective doping profiles and material compositions in different regions of the FinFET structure, particularly in the fin and gate regions, to locally optimize electrical characteristics. This local quality adjustment helps control carrier distribution and potential barriers, mitigating DIBL effects while maintaining short channel dimensions for high density.
3Quantity of substance
If transistor dimensions are reduced to increase integration, then device density improves, but contact resistance increases
Solution Approach 1:
The vertical FinFET structure provides extended vertical surfaces for source and drain contacts, increasing the effective contact area without increasing the lateral device footprint. This dimensional change allows maintaining low contact resistance despite reduced transistor dimensions, as the vertical contact interfaces offer larger surface area for current flow.
Data Source
AI summary
Some embodiments include transistor-containing constructions having gate material within an opening in a semiconductor material and spaced from the semiconductor material by gate dielectric material. The opening has a wide lower region beneath a narrow upper region. A saddle region of the gate dielectric material extends outwardly from a bottom of the opening and is along the semiconductor material beneath the opening. A saddle region of the gate material extends outwardly from the bottom of the opening and is along the gate dielectric material beneath the opening. Source/drain regions are within the semiconductor material along sides of the gate material. Some embodiments include memory arrays.