Tri-Gate Orthogonal Channel Transistor Without Charge Tunneling
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Solution Overview
Problem
Flash memory devices suffer from performance degradation over time due to cumulative damage to the tunneling dielectric, leading to a need for a nonvolatile memory device with longer endurance.
Innovation Solution
A semiconductor device using a metal oxide semiconductor channel layer with three gate electrodes and dual semiconductor channels, providing both horizontal and vertical electrical current paths, and storing electrical charges without charge tunneling, thus enhancing reliability and endurance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If flash memory devices use charge tunneling for nonvolatile storage, then data retention is achieved, but device performance degrades over time due to cumulative damage to the tunneling dielectric
Solution Approach 1:
The patent extracts and eliminates the charge tunneling mechanism from the memory device architecture. By removing the tunneling dielectric layer and the associated charge trapping mechanism, the invention avoids the cumulative damage that occurs during repeated write/erase cycles, thereby improving endurance while maintaining nonvolatile storage capability through a different physical mechanism (floating gate electrode charge storage)
Solution Approach 2:
The patent replaces the durable but damage-prone tunneling dielectric structure with a simpler floating gate electrode structure that can be repeatedly charged and discharged without degrading the underlying dielectric. The floating gate acts as a disposable charge storage element that can be recharged indefinitely, improving device longevity
2Ease of manufacture
If conventional planar transistor structures are used, then manufacturing is simpler, but device performance and scalability are limited
Solution Approach 1:
The patent transitions from a conventional planar (2D) transistor structure to a three-dimensional FinFET structure where the channel is formed as a vertical fin. This dimensional change increases the effective channel area and improves gate control over the channel, enhancing device performance and scalability while remaining compatible with standard semiconductor manufacturing processes
Solution Approach 2:
The patent implements a nested structure where the floating gate electrode is positioned within the FinFET structure, surrounded by the gate dielectric and controlled by the gate electrode. This nested arrangement allows multiple functional elements to be integrated in a compact three-dimensional configuration, improving performance without proportionally increasing manufacturing complexity
Data Source
AI summary
A semiconductor device includes a metal oxide semiconductor channel layer, a first gate dielectric layer contacting a first portion of a major surface of the metal oxide semiconductor channel layer, a first gate electrode overlying the first gate dielectric layer and contacting a second portion of the major surface of the metal oxide semiconductor channel layer, a drain region and a backside gate dielectric layer contacting another major surface of the metal oxide semiconductor channel layer, a backside gate electrode contacting the backside gate dielectric layer, a second gate dielectric layer contacting an end surface of the metal oxide semiconductor channel layer, a second gate electrode contacting a surface of the second gate dielectric layer, and a source region contacting another end surface of the metal oxide semiconductor channel layer.